Sr or Staff ASIC Digital Design Engineer

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities, meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

Senior/Staff Digital Design Engineer

Seeking a highly motivated and innovative experienced Digital Design Engineer with knowledge of ASIC development flow. The candidate will be working as part of a highly experienced mixed-signal design and verification team, targeting next generation of our flagship PCIe and Ethernet PAM4 and NRZ PHY products.

PHY design development is very dynamic and provides an endless list of challenges. The candidate would undergo initial training by top experts in the field followed by continuous on the job training and assignments. The work is very challenging, with new and interesting mixed signal design aspects to address frequently. These technological challenges will continue to bring on additional responsibilities and task ownership.

Key Qualifications

• Relevant digital design experience in the industry
• Scripting experience in Shell, Perl, Python or TCL is a plus.
• Good theoretical and practical understanding of digital signal processing and data recovery circuits.
• Excellent analytical skills to resolve challenges in creative ways and exercise unaided judgment in selecting methods and techniques to obtain solutions.
• Good communication skills for interacting with different design groups (example analog, P&R…) and customers.
• Must be self-motivated, proactive, and able to balance good design quality while meeting tight deadlines.
• Must exhibit ability to produce good results as an individual and team contributor.

Required Experience

• RTL coding, modeling of analog blocks, and/or writing complex system-level tests in Verilog or System Verilog
• Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools.
• Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures.
• Enhancing and maintaining existing SERDES PHY IPs supporting many protocols.
• Interacting with Application Engineers and/or customers to resolve complex technical issues

Unique opportunities presented with this position

• To grow and manage design of product end-to-end.
• Cross-functional learning and interaction with senior internal and external experts across domains
• Have an impact on the new product architectures, quality and development strategies
• Customer-facing role working in close collaboration with pre and post-sales team
• Develop systematic ways to address new problems, think outside of the box

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.