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ASIC Digital Design Verification, Staff Engineer

pin icon Delhi, National Capital Territory of Delhi, India
Noida, Uttar Pradesh, India Apply Now
Category: Engineering Hire Type: Employee
Job ID 50628BR Date posted 06/12/2024

The candidate will be part of the R&D in Solutions Group in India. The position offers learning and growth opportunities.
This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in a role that will include IP Design Verification using UVM based environment methodology.

Job Description:
The candidate will be part of the Synopsys CXL IP Design verification R&D team at Synopsys. You will own UVM based verification environment, which handles multiple features of IP, test plan creation,
test case writing, random constraint creation, coverage closure, SVA and Release. As part of the work, you will closely work with lead and be part of a global team of experienced Engineers.

Technical Expertise Needed:

BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas:
  • Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP/SoC.
  • Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI,APB,AHB) etc
  • Good knowledge of System Verilog.
  • Hands-on experience with coverage closure and writing SVA for IP/SOC.
  • Good simulation debugging skills.
  • Experience with Perforce or similar revision control environment.
  • Experience with Python/TCL or any scripting knowledge is an added advantage.
Job Responsibilities include -
  • Understand Standard Specifications, create testplan for the product and create UVM based testbench architecture. Propose and enhance the UVM architecture with unique idea for verification.
  • Be single point of contact with hands-on experience on all verification tasks – Testbench Creation – Testplan creation – Coverage closure – SVA – Release
  • Perform peer review of testbench code for continuous quality.
  • Own simulation debugs using DVE/Verdi, interact with Design Team and aid in debug and Verification closure.
  • Periodically publish technical papers and/or file patents on the feature updates/innovation carried out.
  • The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide.
  • In addition, the candidate should have excellent oratory and written communication skills in English, should be a team player and possess good problem-solving skills and show high levels of initiative.

This position requires prior industry experience and is not open for college fresh grads.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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Synopsys Hiring Process 1. Apply. As an applicant, your resume, skills, and experience are being reviewed for consideration. 2. Phone screen. Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. 3. Interview. You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via zoom. 4. Offer. Congratulations! You have been selected as a finalist; your recruiter will reach out to propose your offer details. A written offer will soon follow. 5. Onboarding. You will be invited to complete new hire documents to ensure you are set-up and prepared for your first day. 6. Welcome. Your hiring manager, team, and an assigned buddy will help you get acclimated. Over the next few weeks, you will receive communications and engagement invitations that will help ramp you up for your future at synopsys

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