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ASIC Verification Solution Lead:

Bengaluru, Karnataka, India Apply Now Job ID 50189BR Date posted 09/06/2024

Duties

Understand Complete ASIC Design Verification Flow and Customize according to end Application.
Build a Complete Verification flow using an existing design from RTL to GDS.
Modify Methodology/Constraints to accommodate our Recommended Verification Flow
Define data trends and build checkers to validate the flow.
Automate Complete Solution, with self-monitoring trend analytics and Regression trends.

Required Qualifications

BS or MS degree in Computer Science, Electrical or Computer Engineering, or Related Field with 7+ years of experience
Knowledge of Digital design verification(Dynamic/Static), Verilog/VHDL and associated verification tools.
Experience in Complete Verification Methodology and understand what’s needed from verification perspective to Signoff a design.
Proven HDL experience in SystemVerilog/HDL/SVA and UVM methodology
Software experience with Python/C++/TCL scripting knowledge

Apply Now

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Synopsys Hiring Process 1. Apply. As an applicant, your resume, skills, and experience are being reviewed for consideration. 2. Phone screen. Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. 3. Interview. You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via zoom. 4. Offer. Congratulations! You have been selected as a finalist; your recruiter will reach out to propose your offer details. A written offer will soon follow. 5. Onboarding. You will be invited to complete new hire documents to ensure you are set-up and prepared for your first day. 6. Welcome. Your hiring manager, team, and an assigned buddy will help you get acclimated. Over the next few weeks, you will receive communications and engagement invitations that will help ramp you up for your future at synopsys

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