Senior Staff Physical Verification Engineer

Category Engineering Hire Type Employee Job ID 11903 Remote Eligible No Date Posted 22/06/2025

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced and proactive professional with a strong technical background in physical design and physical verification at the IP, block, and full-chip levels. You excel in addressing challenges associated with advanced FinFET and GAA processes and have a proven ability to deliver high-quality results in complex design environments. Your expertise spans RTL-to-GDS implementation, physical verification, and signoff methodologies, and you are adept at collaborating with cross-functional teams to achieve optimal design solutions.

You are detail-oriented, innovative, and thrive in a collaborative environment where continuous improvement is valued. Your strong communication skills enable you to effectively engage with internal teams and external customers, ensuring alignment and success in project execution. With a passion for technology and a commitment to excellence, you are eager to contribute to the development of cutting-edge semiconductor solutions that shape the future.

What You’ll Be Doing:

• Conceptualizing, designing, and productizing state-of-the-art RTL-to-GDS implementations for SLM monitors using ASIC design flows.
• Designing on-chip Process, Voltage, Temperature, Glitch, and Droop monitors to track silicon biometrics.
• Performing physical verification tasks, including DRC, LVS, PERC, ERC, ESD, EM, and antenna cleaning.
• Collaborating with the Place & Route team to resolve full-chip/IP/block-level layout integration issues and drive physical verification closure.
• Coordinating with internal IP owners to address IP-related issues and with the manufacturing team to resolve DRC-related challenges.
• Creating and updating flows/methodologies in collaboration with architects and circuit design engineering teams.

The Impact You Will Have:

• Accelerating the integration of next-generation intelligent in-chip sensors and analytics into cutting-edge technology products.
• Optimizing performance, power, area, schedule, and yield across semiconductor lifecycle stages.
• Enhancing product reliability and differentiation in the market while reducing risk.
• Driving innovation in physical verification and signoff design methodologies and tools.
• Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions.
• Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies.

What You’ll Need:

• Educational Background: BS/B.Tech or MS/M.Tech in Electrical Engineering with 5+ years of relevant industry experience.
• Technical Expertise:
  • Strong experience in physical verification and signoff, including DRC, LVS, DFM, ANT, ERC, ESD, EM, and PERC cleaning.
  • Proficiency with digital design tools from any EDA vendor, preferably Synopsys tools like FC and ICV.
  • Solid understanding of physical design, physical verification, and signoff concepts.
  • Proven track record of successful physical verification closure and tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm, 3nm, 2nm).
  • Experience with design methodologies, including developing custom scripts and enhancing flows for better execution (TCL/PERL scripting required).
• Additional Skills:
  • Exposure to floorplan and PnR flows and tools such as ICC2/FC/Innovus is an added advantage.
  • Good understanding of reliability physics, including EM, ESD, crosstalk, shielding, latch-up, and deep sub-micron challenges.

Who You Are:

• Proactive and detail-oriented with excellent problem-solving skills.
• Adept at working independently and providing physical verification and signoff solutions.
• A strong communicator and teamer, capable of collaborating effectively with diverse teams.
• An innovative thinker with a passion for technology and continuous improvement.
• Committed to delivering high-quality results and achieving project goals.

The Team You’ll Be A Part Of:

You will join a dynamic and collaborative team of engineers focused on developing cutting-edge semiconductor solutions. The team works on advanced physical verification methodologies, physical design, and signoff processes, driving innovation and excellence in the development of next-generation technology products. Together, you will tackle complex challenges, push the boundaries of technology, and contribute to the success of Synopsys' industry-leading solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.