Layout Design, Engineer

Category Engineering Hire Type Employee Job ID 10412 Remote Eligible No Date Posted 06/04/2025

You Are:
 An enthusiastic and detail-oriented Analog & Mixed-Signal (A&MS) Layout Design Engineer eager to make a significant impact in the field of semiconductor design. You have a strong foundation in Electrical Engineering, Computer Science, Physics, or a related discipline, with a keen interest in advanced process nodes and FinFET technology. Your analytical and problem-solving skills are exceptional, and you thrive in collaborative environments, effectively communicating with cross-functional teams. With a deep understanding of layout techniques, signal integrity challenges, and verification methodologies, you are proficient in using EDA tools for layout design and verification. Your familiarity with scripting languages like Python, Tcl, or SKILL for layout automation is an added advantage. As a proactive and independent worker, you are also a team player, ready to engage with senior experts and contribute to innovative IP development.

What You’ll Be Doing:
   •  Designing and developing analog and mixed-signal layouts for high-performance silicon chips.
   •  Collaborating with cross-functional teams to meet project requirements and deadlines.
   •  Utilizing EDA tools for layout design, verification, and ensuring compliance with DRC, LVS, ERC, and PERC methodologies.
   •  Addressing signal integrity challenges and implementing robust layout techniques to meet ESD, latch-up, and antenna requirements.
   •  Automating layout processes using scripting languages like Python, Tcl, or SKILL.
   •  Executing layout projects under the guidance of layout leads and contributing to memory IP development.

The Impact You Will Have:
   •  Enhancing the performance and reliability of silicon chips through meticulous layout design.
   •  Driving innovation in memory IP development, contributing to Synopsys' leadership in the semiconductor industry.
   •  Improving design efficiency and accuracy through automation and advanced verification techniques.
   •  Ensuring the successful integration of Synopsys IP into customer designs, meeting their specific needs and standards.
   •  Collaborating with global teams to share knowledge and best practices, fostering a culture of continuous improvement.
   •  Building strong professional networks with internal and external experts, enhancing Synopsys' technological capabilities.

What You’ll Need:
   •  Bachelor’s or higher degree in Electrical Engineering, Computer Science, Physics, or a related discipline.
   •  Strong analytical and problem-solving skills.
   •  Excellent communication skills and ability to collaborate with cross-functional teams.
   •  Good understanding of FinFET technology and advanced process nodes.
   •  Knowledge of layout techniques to meet ESD, latch-up, and antenna requirements.
   •  Experience with signal integrity challenges in A&MS layout design.
   •  Proficiency in using EDA tools for layout design and verification.
   •  Solid knowledge of DRC, LVS, ERC, and PERC verification methodologies.
   •  Familiarity with Python, Tcl, or SKILL scripting for layout automation is a plus.
   •  Proficiency in verbal and written English to collaborate effectively with global teams.
   •  Experience in analog layout design, specifically MTP, OTP, or other types of memory layout.
   •  Hands-on experience with full Test Chip place-and-route (P&R) is a plus.
   •  Ability to execute layout projects under layout lead guidance.
   •  Experience with CAD tool development for layout automation is a plus.
   •  Ability to work independently while collaborating effectively within a team.
   •  Strong networking skills to engage with senior internal and external experts in the field.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.