Alternate Job Titles:

• Senior Cell Library Design Engineer
• Senior Logic Library Design Engineer
• Senior Standard Cell Designer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced Standard Cell Library Design Engineer with a passion for innovation and technology. You hold a Bachelor's or Master's degree from a reputable university and have over three years of experience in designing standard cell libraries. Your expertise extends to optimizing standard cell circuits to achieve superior performance, power, and area (PPA). You have designed complex circuits such as flip-flops, clock gating cells, level shifters, and power gating cells. Your deep understanding of CMOS device characteristics and design rules in submicron process nodes, especially in FINFET/GAA technologies, sets you apart. You are proficient in running high sigma variation analysis and have a knack for layout design and optimization. Your analytical and logical skills are exemplary, and you thrive in a collaborative environment, working effectively with geographically distributed R&D teams. If you are driven by innovation and eager to contribute to groundbreaking technology, we want to meet you.

What You’ll Be Doing:

• Designing and optimizing standard cell libraries to achieve targeted PPA.
• Developing complex circuits including flip-flops, clock gating cells, level shifters, and power gating cells.
• Collaborating with layout designers to optimize layout parasitics.
• Engaging in layout extraction and understanding layout-dependent parameters.
• Conducting timing and power characterization of standard cells.
• Working closely with cross-functional teams for optimization across the design chain.

The Impact You Will Have:

• Enhancing the performance, power, and area of standard cell libraries.
• Contributing to the development of high-impact, cutting-edge technology.
• Driving innovation in complex circuit design and optimization.
• Ensuring the successful integration of IP blocks into SoCs.
• Influencing the design and development of self-driving cars, AI, and IoT devices.
• Supporting Synopsys’ leadership in the silicon IP market.

What You’ll Need:

• Bachelor's or Master's degree in Electrical Engineering or related field.
• 3+ years of experience in standard cell library design.
• Expertise in CMOS device characteristics and submicron process nodes.
• Proficiency in designing complex circuits and running high sigma variation analysis.
• Experience in layout design and optimization.

Who You Are:

• Strong analytical and logical thinker.
• Detail-oriented with excellent problem-solving skills.
• Effective communicator and collaborator.
• Innovative and passionate about technology.
• Adaptable and able to work in a dynamic, fast-paced environment.

The Team You’ll Be A Part Of:

You will join the Logic Library Group, a dynamic team focused on developing high-performance standard cell libraries. The team collaborates closely with other R&D groups to optimize the entire design chain and deliver cutting-edge technology solutions. Together, you will work on innovative projects that drive the future of chip design and integration.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.