ASIC Digital Design, Engineer

About Synopsys:

Synopsys technology is at the heart of innovations that are changing the way people work and play. Self-driving cars. Machines that learn. Lightning-fast communication across billions of devices in the datasphere. These breakthroughs are ushering in the era of Smart Everything―where devices are getting smarter and connected, and security is an integral part of the design.

Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high performance multi-rate transceiver portfolio for high-end networking and high performance computing applications. The area-efficient PHY provides a low active and standby power solution that supports multiple electrical standards, including PCI Express® (PCIe®) 6.0, 1G to 112Gbps electrical PHY for 400G/800G Ethernet, Cache Coherent Interconnect for Accelerators (CCIX), Compute Express Link (CXL), JESD204C, CPRI, SATA, and other industry-standard interconnect protocols. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 112G PHY delivers signal integrity and jitter performance that exceeds the standards electrical specifications.

Job Description:

We are looking for a highly motivated Engineer who shall be responsible for the verification of multi-protocol 112G PHY IP.  The responsibilities include:

• Be a technical expert in one or more interface protocols (Eg: Ethernet, PCIe, etc). This expertise helps in development, verification, silicon validation & customer support.
• Review SERDES / PHY / Controller IP specification & validate compliance to protocol of interest.
• SV verification of SERDES / PHY IPs internally developed. Responsibility includes
  • Verification plan development and review.
  • Verification environment development. UVM knowledge preferred.
  • RTL, GLS & Co-simulations & coverage closure (Functional + Code)
  • Deliver high quality RTL and other simulation models to customer.
  • Verification using VIP for the protocol of interest.
  • Simulation bring-up of protocol sub-system with SERDES + Controller for the protocol of interest. 
  • Own support of customers with bring-up of IP in customer simulation environment. Develop, deliver and support customer with any SV verification components they might need for the IP for integration into their simulation environment. When customer silicon is available, support customer with silicon bring-up and debug of issues.
  • Bring-up and demonstrate Testchip+FPGA system demo for the protocol of interest to customers & also in conferences.

Requirements

• B.Tech/M.Tech with 5+ years of relevant experience
• Work Experience in interface protocols - Ethernet, PCIe, CXL, JESD, CPRI is highly preferred.
• Experience of functional verification flow, Verification tools, and methodologies VMM, OVM/UVM and System Verilog
• Experience with System Verilog Assertions, code and functional coverage implementation and review
• Fundamental knowledge of Analog and Digital mixed signal design
• Scripting and automation using Perl/Python
• Excellent debug and diagnostic skills

Inclusion and Diversity are important to us at Synopsys. Synopsys considers all applicant for employment without regard to race, color, religion, national origin, gender, sexual o

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.