Applications Engineering, Staff Engineer
Shanghai, Shanghai Municipality, ChinaShenzhen, Guangdong, China Apply Now
Category: Engineering
Hire Type: Employee
Job ID 50419BR Date posted 06/03/2024
Job Description:
Description
This position requires a highly motivated and experienced individual to work with Synopsys’ customers on integrating leading edge Interface IP (IIP) into their ASIC SoC/systems for next generation products. IIP includes Serdes PHYs and Controllers.
The position offers opportunities to work on Synopsys IIP and the latest industry specifications/applications on various hot market segments. The position will provide IIP integration guidance to customers throughout their SoC flow to resolve technical challenges, perform integration reviews at key milestones and support silicon/system bring-up. Occasional travels will be required.
Responsibilities Include
Education and Experience
Apply Now
Description
This position requires a highly motivated and experienced individual to work with Synopsys’ customers on integrating leading edge Interface IP (IIP) into their ASIC SoC/systems for next generation products. IIP includes Serdes PHYs and Controllers.
The position offers opportunities to work on Synopsys IIP and the latest industry specifications/applications on various hot market segments. The position will provide IIP integration guidance to customers throughout their SoC flow to resolve technical challenges, perform integration reviews at key milestones and support silicon/system bring-up. Occasional travels will be required.
Responsibilities Include
- Understand IIP applications on customer specific SoC and systems
- Keep abreast of the latest ASIC/SoC design flows and EDA tools
- Provide expert advice and support to configure and resolve IIP integration challenges including simulation, synthesis, floorplan, STA, DFT, silicon bring-up, etc.
- Provide integration training to customers and conduct reviews on their major SoC milestones
- Provide feedback to Synopsys R&D for continuous IIP product improvements
- Participate in IIP R&D design reviews to align development with future customer needs
Education and Experience
- Bachelors and/or Masters Degree in Electrical and/or Electronic Engineering, Computer Engineering or Computer Science
- Minimum 5 years of IIP and/or ASIC Design/Verification/Applications experience required
- Hands-on experience on RTL coding in Verilog, simulation, synthesis, static timing analysis, equivalence check, etc. Experience on CDC/Lint, DFT are plus.
- Domain knowledge in Display Protocol (HDMI/DP/MIPI DSI) is preferred but optional.
- Experienced with ASIC/SoC tape-out from concept to full production is desirable
- Silicon debug and troubleshooting skills are highly desirable
- Creative, results oriented with the ability to manage multiple tasks concurrently
- Good verbal and written communication skills in English and ability to interact with customers
- High degree of self-motivation and personal responsibility
- Strong analytical, reasoning and problem-solving skills, and attention to details
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View all job opportunities here
View all job opportunities here