In this role you will be responsible for digital implementation from RTL to GDS2, which includes the following stages:
 * Gate level netlist synthesis
 * Physical implementation
 * Static Timing Analysis
 * EMIR
 * Physical verification
 * Signoff

 Key Qualifications
 * Possesses relevant experience in deep submicron CMOS technologies and ASIC digital implementation
 * Knowledge of the full design cycle from RTL to GDSII
 * Good software and scripting skills, version control, understanding of CAD automation methods.
 * Good written and verbal communication in English
 * Teamwork or Network relation experiences
* Problem-solving and organizational skills
 * Academic and practical exposure in the following fields: high-speed design, low-power design, high-speed clock design and distribution, timing closure, signal integrity
* Requires a degree in Electrical or Computer Engineering with specialization in Micro-electronics (or equivalent)

 Preferred Experience
 * 2+ years of relevant work experience.
 * ASIC design methodology experience in back-end flows of digital and Mixed Signal circuit design.