ASIC Digital Design, Sr Engineer

Seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. The candidate would be working as part of a highly experienced mixed-signal design and verification team, helping deliver highest quality IP releases to customers for the next generation NRZ and PAM-based SerDes products. Good theoretical understanding in high-speed serializer and data recovery circuits is a plus. The position offers an excellent opportunity to work with an expert team of digital and mixed-signal engineers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on prototype test-chips.

The PHY IP development is very dynamic and provides an endless list of challenges. The candidate would have an initial training done by the top experts in the field as well as continuous on the job training and assignments. The work is very challenging, not only given the constant technological changes but also given the ownership and the need to charter unknown waters.

Key Qualifications

• BSEE or MSEE plus a minimum of 2 years of digital design and/or verification experience in the industry
• Must be familiar with Verilog and VCS.
• Good knowledge and working experience of synthesis tools DC/FC and PT is required
• Must have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows
• Good Knowledge and Experience in Spyglass/VC-Spyglass.
• Experience in Core Assembler flow to create, verify and use Core Kit views for IPs
• Scripting experience in Shell/Perl/Python/TCL is a strong plus.
• Good communication skills for interacting between different design groups and customer support teams are required.
• Must be self-motivated, proactive, and able to balance good design quality while meeting tight deadlines
• Resolves issues in creative ways and exercises independent judgment in selecting methods and techniques to obtain solutions
• May guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise
• Must exhibit ability to produce good results as an individual and team contributor

Preferred Experience

• Defining synthesis design constraints and resolving STA issues as well as gate-level simulation failures
• Defining Clock/Reset domain crossing design constraints and evaluating violations using CDC/RDC tools
• Enhancing and maintaining existing SERDES PHY IPs supporting multiple protocols
• Creating, verifying and using Core-Kit views in Core Assembler flow.