Lead RTL Design Engineer

The candidate will be part of the R&D in Solutions Group at our Bangalore Design Center, India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in a role that will include IP Design using latest HDL and design Flows .

Job Description
The candidate will be part of the Synopsys IP Design R&D team at Synopsys. The candidate will be expected to specify, design/architect and implement state-of-the-art Verification environments for the Synopsys family of synthesizable cores and perform Verification tasks for the IP cores. The candidate will work closely with RTL designers and be part of a global team of expert Verification Engineers.
Will be working on the next generation AMBA protocols for commercial, Enterprise and Automotive applications
Job Responsibilities -

• Will be working on the next generation AMBA standards, DMA Controller and Serial protocols for commercial, Enterprise and Automotive applications
• Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create architecture and micro-architecture with detailed design documents for some of the components of the design for medium to high complexity functionality.
• Be an individual contributor in the Design Tasks – RTL coding of design, synthesis, CDC analysis, debug, Test development etc.
• May need to interact with customers to discuss/ understand customers’ specification requirements, if needed .
• The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.

Must have BSEE in EE with 8+ years of relevant experience or MSEE with 7+ years of relevant experience in the following areas:

• Knowledge of one or more of protocols: AMBA (AMBA2, AXI), SD-MMC, MIPI-I3C/UFS/Unipro, Ethernet, DDR, PCIe, USB
• Hands on experience with architecting/ micro-architecture/ detailed design from Functional Specifications. Must have worked on control path oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design, etc.
• Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools
• Lint, CDC, Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background.
• Experience with Scatter Gather DMA design, exposure to SPI/I2C/I2S serial controller interface is a significant plus.
• Experience with Perforce or similar revision control environment
• Knowledge of Perl/Shell scripts.
• Exposure to quality processes in the context of IP design and verification is an added advantage
• Ability to work/ Prior experience as a Technical Lead for a small team is a major plus.

In addition, the candidate should have good communication skills, should be a team player and possess good problem solving skills and show high levels of initiative.
This position requires prior industry experience and is not open for college fresh grads.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.