Mgr II, A&MS Layout Design

Bengaluru, Karnataka
Hyderabad, Telangana India Apply Now Job ID 47836BR Date posted 01/02/2024

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

We're looking for Analog Mixed Signal Layout Designer to join our Hyderabad team. Does this sound like a good role for you? Synopsys High-speed SERDES layout team is looking for a highly motivated and innovative engineer with strong base level understanding on Analog and mixed signal layouts. You will be working as part of a highly experienced mixed-signal layout team and will be responsible for designing the physical layout of custom analog and digital blocks under the guidance of experienced layout engineers. Our environment is best in class with full suite of IC design tools supplemented by custom, in-house tools supported by an experienced CAD team. The position offers an excellent opportunity

Mgr II, A&MS Layout Design

Role and Responsibilities

In this Role, you will be working with local and global teams in developing layout for High-speed, complex mixed-signal designs in latest technology nodes.

As a Manager of Solutions IP Design Group, we are looking for:

Hands-on technical experianced individual who has a depth and breadth of knowledge in various technology nodes (Planar, FinFET and GAA) across different foundries in last 10+ yrs with a good silicon successs track record
8+ yrs of experience, particularly in High Speed SERDES layout development (> 32G data rate), preferably in latest FinFET nodes.
Experience in managing multiple layout projects, executed in parallel from floorplan till GDS release, while ensuring quality checks are taken care at all stages of layout development.
Experience in working with engineers and contractors within local and global team of dfiferent time zones.
Experience in working with other internal cross team’s i.e., Digital Integration team, CAD Team, Methodology team, etc., in a clear, systematic way to ensure deliverables and smooth running of project at all times.
Experience in understanding project goals, define a clear layout scope, milestones, resource plan at intial stage of development and to track the execution schedule at development stage, and to have contigency plans at all the times to ensure smooth delivery.

Key Qualifications

Bachelor or Master’s degree in VLSI engineering or similar field like ECE, EEE or EIE.
15+ yrs of Total Experience, Out of which atleast 8+ yrs in High Speed SERDES development.
Hands on Experience in high speed layout development from floorplan till GDS release.
Familiarity with Analog Design Flow, Co-sim Flow and Digital design and verification flow.
Understanding of programming skills in languages such as C, Perl, Python, TCL
Experience in working with Microsoft tools like Powerpoint, Excel, etc., by creating corporate level presentations.
Strong passion and ability to attract, hire, retain engineers by motivating them and by inculcating innovation culture.