SOC Engineering, Sr Staff Engineer
Taiwan Minsucun, Taiwan, Taiwan
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Category: Engineering
Hire Type: Employee
Job ID 50409BR Date posted 05/22/2024
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
In the System Solutions Group we are shaping solutions for dependable systems, requiring safety, security, reliability, low power and more. Our team works with customers and industry partners to understand their needs and identify technical requirements. We are passionate about methodologies and automation: we collaborate with customers to make their job easier when they develop their products.
Signal/Power Integrity Engineer (3DIC)
Job Description:
This job is for a 3DIC Packaging design engineer with emphasis on SI/PI simulations. In this role, the engineer will be a part of a team that designs cutting edge packaging solutions for industry’s leading 3DIC customers in the datacenter, AI/ML space. The candidate will evaluate the design tradeoffs by running Signal and Power Integrity simulations to ensure the design is ready for sign-off. An in-depth understanding of Signal integrity fundamentals is required to successfully architect plans for modeling of multiple devices with several high-speed interfaces on the silicon interposers and between chiplets. Need to be an expert on setting up test-benches and running frequency, transient and channel simulations. Need to work cross functionally with Synopsys’ IP teams to translate the industry’s largest IP portfolio of memory and SerDes IP’s electrical specifications into design requirements. The ideal candidate should be self-motivated, detail-oriented, and have strong coordination and partnership skills.
Qualifications:
nThe minimum qualifications for this position include an MS/Ph.D. degree in Electrical Engineering.
nWith 10+ years of experience in Signal and Power Integrity field
nStrong knowledge of Signal Integrity fundamentals (PDN, EMIR, Basic Analog circuits, Transmission Line theory, Xtalk, S-parameters, channel simulations)
nPerformed chip-level PDN analysis using Redhawk for EM-IR (both static and Dynamic), generated CPM models, etc…
nExpertise in the Electromagnetics field with 5+ years of hands-on experience using 2.5D and 3DFEM solvers such as SiWave and HFSS.
nSystem-level power integrity simulation: VRM + PCB + PKG + Interposer + Stacked dies. Has used tools like SiWave to extract PCB/Pkg models and optimized decoupling capacitors. Has run both frequency and time domain simulations to analyze impedance and ripple.
nThrough understanding of digital and analog equalization techniques such as CTLE, FIR, DFE, FFE and be able to use AMI models to setup channel simulations and be able to analyze the results to improve channel routings.
nIn addition to the mentioned qualifications, candidates with a demonstrated ability to devise innovative design solutions will be highly valued.
Preferred qualifications:
n Performed SI/PI simulations for HBM2+, UCIe and other chiplet and silicon interposer interfaces.
nExperience with 2/2.5D and/or 3D integration chip design projects
nUnderstand ESD design and ran simulations using tools like Pathfinder to check for ESD sign-off at die + package.
nThe ideal candidate should have evidence of strong organizational and planning skills for engineering projects and possess good communication and presentation skills for executive project coordination.
nThe candidate should also have experience working with multiple function teams for EDA tool collaboration.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Apply Now
In the System Solutions Group we are shaping solutions for dependable systems, requiring safety, security, reliability, low power and more. Our team works with customers and industry partners to understand their needs and identify technical requirements. We are passionate about methodologies and automation: we collaborate with customers to make their job easier when they develop their products.
Signal/Power Integrity Engineer (3DIC)
Job Description:
This job is for a 3DIC Packaging design engineer with emphasis on SI/PI simulations. In this role, the engineer will be a part of a team that designs cutting edge packaging solutions for industry’s leading 3DIC customers in the datacenter, AI/ML space. The candidate will evaluate the design tradeoffs by running Signal and Power Integrity simulations to ensure the design is ready for sign-off. An in-depth understanding of Signal integrity fundamentals is required to successfully architect plans for modeling of multiple devices with several high-speed interfaces on the silicon interposers and between chiplets. Need to be an expert on setting up test-benches and running frequency, transient and channel simulations. Need to work cross functionally with Synopsys’ IP teams to translate the industry’s largest IP portfolio of memory and SerDes IP’s electrical specifications into design requirements. The ideal candidate should be self-motivated, detail-oriented, and have strong coordination and partnership skills.
Qualifications:
nThe minimum qualifications for this position include an MS/Ph.D. degree in Electrical Engineering.
nWith 10+ years of experience in Signal and Power Integrity field
nStrong knowledge of Signal Integrity fundamentals (PDN, EMIR, Basic Analog circuits, Transmission Line theory, Xtalk, S-parameters, channel simulations)
nPerformed chip-level PDN analysis using Redhawk for EM-IR (both static and Dynamic), generated CPM models, etc…
nExpertise in the Electromagnetics field with 5+ years of hands-on experience using 2.5D and 3DFEM solvers such as SiWave and HFSS.
nSystem-level power integrity simulation: VRM + PCB + PKG + Interposer + Stacked dies. Has used tools like SiWave to extract PCB/Pkg models and optimized decoupling capacitors. Has run both frequency and time domain simulations to analyze impedance and ripple.
nThrough understanding of digital and analog equalization techniques such as CTLE, FIR, DFE, FFE and be able to use AMI models to setup channel simulations and be able to analyze the results to improve channel routings.
nIn addition to the mentioned qualifications, candidates with a demonstrated ability to devise innovative design solutions will be highly valued.
Preferred qualifications:
n Performed SI/PI simulations for HBM2+, UCIe and other chiplet and silicon interposer interfaces.
nExperience with 2/2.5D and/or 3D integration chip design projects
nUnderstand ESD design and ran simulations using tools like Pathfinder to check for ESD sign-off at die + package.
nThe ideal candidate should have evidence of strong organizational and planning skills for engineering projects and possess good communication and presentation skills for executive project coordination.
nThe candidate should also have experience working with multiple function teams for EDA tool collaboration.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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