R&D Engineering, Principal Engineer

Category Engineering Hire Type Employee Job ID 16981 Date Posted 04/14/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned engineering leader with a passion for innovation and a deep understanding of physical design methodologies for cutting-edge semiconductor technologies. With a proven track record of successful project tape-outs, you thrive in collaborative, multidisciplinary environments, and you enjoy mentoring and guiding teams to achieve ambitious technical goals. You are comfortable leading initiatives from RTL through GDSII, leveraging your expertise to navigate complex challenges and deliver industry-leading solutions.

Your experience spans advanced FinFET nodes and the latest SERDES standards, and you possess a nuanced appreciation for both digital and mixed-signal architectures. You are methodology-driven, adept at software and scripting, and you have a strong grasp of CAD automation. Communication is your forte, whether you’re interfacing with peer groups, customers, or cross-functional teams. You embrace autonomy, make timely decisions, and adapt quickly to changing priorities. Your leadership ensures projects are delivered on schedule, meeting or exceeding power, area, and performance targets. You relish the opportunity to work on high-impact technology at the forefront of the semiconductor industry, and you’re eager to contribute to Synopsys’ ongoing success.

What You’ll Be Doing:

• Leading the physical implementation of advanced high-speed interface IPs and test-chips, from RTL to GDSII.
• Driving project execution for SERDES developments (56G/112G/224G PAM4/6) across multiple process nodes, including the latest FinFET technologies.
• Collaborating closely with front-end, analog, CAD, and product teams to ensure seamless integration and sign-off.
• Managing and mentoring a small team of engineers, fostering a culture of excellence, innovation, and continuous improvement.
• Developing and refining timing constraints and design architectures to ensure on-time delivery and optimal power/area targets.
• Applying advanced low-power design techniques and addressing the challenges of analog/digital interfaces in complex mixed-signal IPs.
• Contributing to methodology enhancements, CAD automation, and process improvement initiatives.

The Impact You Will Have:

• Elevate Synopsys’ leadership in high-speed SERDES IP and mixed-signal solutions for next-generation silicon.
• Accelerate time-to-market for advanced interface IPs by ensuring robust and efficient physical implementation flows.
• Drive innovation in low-power and high-performance design, influencing industry standards and best practices.
• Mentor and empower engineering talent, building a high-performing team that delivers exceptional results.
• Strengthen cross-functional collaboration, optimizing integration and sign-off processes across technology domains.
• Enhance customer satisfaction through technical excellence, timely delivery, and superior product quality.

What You’ll Need:

• 12+ years of digital or physical design experience, with significant contributions to project tape-outs as a technical driver or lead.
• Expertise in the full design cycle from RTL to GDSII, including chip-level implementation and sign-off.
• Hands-on experience with advanced FinFET nodes (TSMC 16nm and below), plus proficiency in low-power design techniques.
• Strong engineering foundation in digital design, architecture, implementation flows, and verification.
• Proficiency in software and scripting languages (Perl, Tcl, Python), with knowledge of CAD automation methodologies.
• Solid understanding of analog/digital interface challenges and mixed-signal verification flows.
• Experience in developing timing constraints and design architectures to meet power and area targets.
• MSEE with 10+ years or BSEE with 12+ years of relevant experience.
• Previous project leadership experience and ability to travel internationally as needed.

Who You Are:

• Exceptional communicator, able to convey complex concepts across peer groups and customers.
• Autonomous and decisive, comfortable making timely decisions in dynamic environments.
• Collaborative, with a strong team orientation and mentoring skills.
• Methodology-driven, detail-oriented, and committed to continuous learning.
• Adaptable, able to manage interruptions and shifting priorities with resilience.
• Customer-focused, striving for technical excellence and satisfaction.

The Team You’ll Be A Part Of:

You’ll join the Mixed-Signal IP organization – a diverse, collaborative group dedicated to developing industry-leading SERDES platforms and interface IPs. The team partners closely with front-end, analog, CAD, and product specialists to deliver innovative solutions for global customers. Together, you’ll drive advancements in high-speed connectivity, low-power design, and silicon integration, shaping the future of semiconductor technology.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.