Principal Engineer, CAD Methodologies

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned engineering professional with a strong background in CAD methodologies and a passion for innovation. With over 12 years of industry experience and a Bachelor’s or Master’s degree in electrical engineering, you have a deep understanding of the ASIC development cycle and full-chip SOC flows. You are well-versed in Synopsys EDA tools used for RTL2GDS flows and excel in developing algorithms and scripts for high-speed, high-performance, and low-power design methodologies. You are familiar with new chip design technologies involving chiplets, D2D interfaces, and 3DIC. Your programming skills in languages such as C, C++, Python, Perl, and TCL are exceptional, enabling you to automate complex processes efficiently. You thrive in a collaborative environment, working seamlessly across functional teams to deliver customer-centric solutions. Your expertise and innovative approach make you an invaluable asset to any project you undertake.

What You’ll Be Doing:

• Providing Process, Voltage, and Temperature recommendations and corner selections for various projects.
• Setting up methodologies for Timing Signoff, including POCV settings, margining methodology (jitter/setup/hold margins), and correlation between implementation and signoff tools.
• Enabling new technologies for design services, including pathfinding for new nodes, Radiation Hardening (A&G programs), and Autograde signoff criteria.
• Owning the methodology and templates for generating timing constraints for all modes.
• Managing Low Power methodologies, UPF template ownership, and ramp-up/ramp-down IR drop analysis.
• Creating and managing methodologies for custom power grids, high-speed custom clock trees, Decap, EMIR, ESD, and Spice analysis of clock trees.
• Supporting ongoing projects with Performance/Power/Area improvements.
• Interfacing with foundries for tapeout-related activities, including PDK/mock-tapeouts/e-job views.

The Impact You Will Have:

• Driving the integration of more capabilities into an SoC—faster.
• Helping customers meet unique performance, power, and size requirements of their target applications.
• Reducing risk and speeding up time-to-market for differentiated products.
• Empowering the creation of high-performance silicon chips and software content.
• Enabling leading-edge customers to complete their most challenging SoC design projects.
• Contributing to innovations that change the way we work and play, including self-driving cars, AI, the cloud, 5G, and IoT.

What You’ll Need:

• Excellent understanding of the ASIC development cycle and full-chip SOC flows.
• Familiarity with all Synopsys EDA tools used for RTL2GDS flows.
• Proficiency in developing algorithms and scripts for high-speed, high-performance, and low-power design methodologies and flows.
• Knowledge of new chip design technologies involving chiplets, D2D interfaces, and 3DIC.
• Exceptional programming skills in languages such as C, C++, Python, Perl, and TCL for automation purposes.
• Extensive experience in partnering across functional teams.
• Experience working in a customer-centric environment.

Who You Are:

You are a proactive and innovative thinker with a collaborative spirit. You have a keen eye for detail and a deep understanding of complex engineering problems. Your ability to communicate effectively with various stakeholders and your passion for continuous learning and improvement set you apart. You thrive in dynamic environments and are always ready to tackle new challenges.

The Team You’ll Be A Part Of:

The Systems Solutions Group (SSG) delivers tool, methodology, architecture, design creation, design verification, and physical implementation expertise to enable leading-edge customers to complete their most challenging SoC design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. Our customers develop SOCs for high-performance computing, automotive, aerospace & defense, and more.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.