Principal CAD Methodologies Engineer

Austin, Texas, United States

Engineering

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Overview

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Principal CAD Methodologies Engineer

Responsibilities:

Process, Voltage and Temperature recommendation and corner selection for a given project.
Setup a methodology for Timing Signoff that includes POCV settings, Margining methodology (jitter/setup/hold margins), correlation between Implementation and signoff tools
New Technologies enablement for design services that include path finding for new node, Radiation Hardening(A&G programs) , Autograde signoff criteria etc
Timing constraints methodology and template ownership for generating timing constraints for all modes
Low Power methodology, UPF template ownership , ramp-up/ramp-down IR drop analysis
HPC – Create and manage methodologies for custom power grid , High speed custom clock trees , Decap , EMIR , ESD , Spice analysis of clock trees
Support ongoing projects with Performance/Power/Area improvements.
Tapeout related foundry interface involving PDK/mock-tapeouts/e-job views etc

Required Skills:

Excellent understanding of the ASIC development cycle and full-chip SOC flows.
Familiar with all the Synopsys EDA tools used for RTL2GDS flows.
Very sound in developing algorithms and scripts for high speed/performance and low power design methodologies and flows.
Familiar with new chip design technologies involving chiplets,D2D interafces,3DIC etc
Exceptional in programming languages(C/C++/Python/Perl/TCL etc) to help with Automation
Extensive experience in partnering across functional teams.
Experience working in a customer centric environment.

Qualifications:

Minimum 12 years of industry experience.
Bachelor’s or Master’s degree in electrical engineering

The base salary range across the U.S. for this role is between $159,000-$239,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

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Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.
Time Away

In addition to company holidays, we have ETO and FTO Programs.
Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
Retirement Plans

Save for your future with our retirement plans that vary by region and country.
Compensation

Competitive salaries.

** Benefits vary by country and region - check with your recruiter to confirm

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Hiring Journey at Synopsys

Apply

When you apply to join us, your resume, skills, and experience are first reviewed for consideration.

Phone Screen

Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have.

Interview

Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role.

Offer

Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept!

Onboarding

There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation.

Welcome!

Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

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