Analog/Mixed-Signal Layout Project Engineer

You will be responsible for the resource and project planning and coordination for the analog layout design teams globally. You will be a go-to person for physical design team planning and multi-IP customer technical discussions. This role will involve close interaction and collaborative teamwork with multiple functional groups (front end, analog, ASIC, CAD) and the product teams globally. The ideal candidate will be an excellent communicator and comfortable managing multiple tasks.

You will be part of an advanced physical design team developing full custom analog and ASIC layout of high-speed integrated circuits. You will be exposed to SerDes PHY design for PCIe, SATA, XAUI, and other protocols. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team.

Ideal background would include hands-on analog layout or ASIC physical design experience with project management background and aptitude.

Responsibilities

• Owns cross team planning, collaboration, and coordination ensuring that geographically distributed teams are well-aligned
• Measure project and performance using appropriate systems, tools and techniques
• Establish and maintain relationships with cross-functional teams, internal and external customers
• Create and maintain comprehensive project documentation

• Familiarity with physical design of analog and mixed signal CMOS circuits
• Exposure and knowledge of the full design cycle from RTL to GDSII, including chip level
• Excellent communication skills, ability to think and communicate at different levels of abstraction, with peer groups as well as customers
• Solid organizational skills including attention to detail and multi-tasking skills
• Autonomous, timely decision maker and able to cope with interrupts
• Experience with advanced FinFET nodes, TSMC 16 nanometer and below
• Exposure to SERDES design architectures, and layout
• Experience with Design tool(s): Custom Compiler, Cadence Virtuoso or equivalent
• Verification tools: ICV, Calibre
• Experience in working with Jira/Atlassian (or other such) tools
• Strong working knowledge of MS Office Suite of applications

• Typically requires MSEE or BSEE with a minimum of 2 years of related experience
• Previous analog layout or ASIC physical design experience
• Solid understanding of digital / mixed signal flows and SOC integration challenges

Solutions Group

The Solutions Group provides high-quality, silicon-proven semiconductor IP solutions for SoC designs. The Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, signal/power integrity analysis, and IP prototyping kits. Synopsys' extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enables designers to reduce integration risk and accelerate time[1]to-market.

About Synopsys
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

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Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.