We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent enough time in ASIC design to know that a clean netlist is only the beginning. The real work starts when you need to close timing at 3nm, manage a routing congestion nightmare, or explain to a customer why their clock tree isn't converging the way they expected. You understand that physical design is equal parts technical depth and customer translation, and you are comfortable living in both.

You understand what is happening under the hood. When a placement strategy fails, you can diagnose whether it is a floorplan issue, a timing constraint problem, or a tool setting that needs adjustment. You have worked through enough tape outs to know which corners matter and which ones are noise.

Working with customers energizes you. You can sit in a design review, absorb what they are actually struggling with, and turn that into a demo or evaluation plan that addresses the real problem, not the surface one. You are organized enough to juggle three customer engagements without dropping threads, and technical enough that engineers trust your recommendations. At Synopsys, you will work with the tools that power the most advanced chip designs in the world, and the customers building them.

What You'll Be Doing

• Support customer evaluations and benchmarks of Synopsys physical design tools including Fusion Compiler and ICC2, running real design flows from placement through routing and timing closure
• Deliver technical demonstrations and training sessions that show customers how to solve specific design challenges at sub-5nm nodes using Synopsys RTL-to-GDSII solutions
• Debug customer design issues involving placement, clock tree synthesis, routing, and advanced timing optimization, working directly with design teams to resolve bottlenecks
• Collaborate with Account Managers to shape technical solutions during account planning, translating customer pain points into tool adoption strategies
• Manage multiple customer activities at once, setting priorities based on account needs, evaluation timelines, and sales cycles
• Build and refine design methodologies that demonstrate best practices for advanced node designs, including AI-driven optimization techniques
• Participate in competitive benchmarking exercises, positioning Synopsys tools against alternatives with data-driven technical comparisons

The Impact You Will Have

• Enable customers to achieve measurable improvements in PPA (power, performance, area) and reduce tapeout schedules by weeks or months through better tool adoption and methodology
• Accelerate design closure at advanced nodes by helping customers navigate complex timing, routing, and congestion challenges with Synopsys solutions
• Drive tool evaluations that convert into long-term customer relationships and expanded Synopsys footprint within strategic accounts
• Contribute technical insights from customer engagements back to product teams, shaping future tool capabilities based on real-world design needs
• Build customer confidence in Synopsys methodology at critical decision points, influencing tool selection and design flow architecture
• Reduce customer support escalations by proactively addressing design issues during evaluations and early adoption phases

What You'll Need

• Bachelor's degree in electrical engineering or equivalent with 4+ years of ASIC design experience, or master's degree with 2+ years of experience
• Hands-on experience with industry-standard place and route tools for physical design implementation, including placement, optimization, clock tree synthesis, and routing
• Working knowledge of Synopsys backend tools such as Fusion Compiler, ICC2, or equivalent P&R platforms from other vendors
• Understanding of RTL-to-GDSII design flows and the interdependencies between synthesis, physical implementation, and timing signoff
• Strong grasp of advanced node design challenges including sub-7nm or sub-5nm methodologies, timing closure techniques, and routing at scaled geometries
• Experience with static timing analysis tools like Primetime is a plus
• Familiarity with logic synthesis tools such as Design Compiler or Fusion Compiler is a plus

Who You Are

• You can walk into a customer meeting, listen to a design problem, and sketch out a technical approach on the whiteboard that makes sense to both the engineer and their manager
• You stay calm when managing three customer evaluations with overlapping deadlines, and you know how to communicate status without creating panic
• You are comfortable saying "I don't know, but I will find out" and then actually following through with a real answer, not a deflection
• You can explain a complex timing optimization tradeoff in two sentences without losing the technical nuance or oversimplifying to the point of uselessness
• You are genuinely curious about how things break, whether it is a routing failure in a customer design or a methodology gap in a competitive benchmark
• You treat customer success as your success, and you measure your work by whether the design actually closed, not just whether the demo looked good

The Team You'll Be Part Of

You will join the Customer Success Group Applications Engineering team in Bangalore, working as a Physical Design Specialist supporting sales and adoption of Synopsys RTL-to-GDSII solutions. The team works closely with Account Managers and customers across multiple geographies, focusing on advanced node design challenges and methodology development. 

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.