ASIC Digital Design, Architect
Overview
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
Job Description
Job Description The candidate will be part of the DesignWare IP Verification R&D team at Synopsys. Person will be expected to specify, design/architect and implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores.
Person will work closely with RTL designers and be part of a global team of professional Verification Engineers. Will be working on the next generation connectivity protocols for Commercial, Enterprise and Automotive applications Job role will have a combination of Test planning, Test environment coding both at unit level and system level, Test case coding, debugging, FC coding and testing, meeting quality metric goals and regression management.
Requirements: Must have BSEE in EE with 20+ years of relevant experience or MSEE with 15+ years of relevant experience in the following areas:
- Must have prior experience in architecting verification environments for complex serial protocols.
- Must have experience in developing HVL (System Verilog) based test environments, developing, and implementing test plans, implementing, and extracting verification metrics such as functional coverage.
- Must have exceptional HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools.
- Must be very proficient in verification methodologies such as VMM/OVM/UVM/ is required.
- Exposure to Formal verification methodologies is highly desirable.
- Knowledge of one or more of protocols: MIPI-I3C/UFS/Unipro, AMBA (AMBA2, AXI), SD/eMMC, Ethernet, DDR, PCIe, USB
- Familiarity with HDLs such as Verilog and scripting languages such as Perl, TCL, Python is highly desired.
- Exposure to IP design and verification processes including VIP development is highly desirable..
- There will be exceptional focus on functional coverage-guided methodology. So, the corresponding mindset is a must.
- It is essential that the person has good written and oral communication skills and can demonstrate good testing, debug and problem-solving skills and show high levels of initiative.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Benefits
At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
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Health & Wellness
Comprehensive medical and healthcare plans that work for you and your family.
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Time Away
In addition to company holidays, we have ETO and FTO Programs.
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Family Support
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
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Retirement Plans
Save for your future with our retirement plans that vary by region and country.
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Compensation
Competitive salaries.
** Benefits vary by country and region - check with your recruiter to confirm
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