ASIC Digital Design, Engineer

• Will be working on the next generation USB/DDR/PCIe/Ethernet protocols for commercial, Enterprise and Automotive applications
• Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create architecture and micro-architecture with detailed design documents for some of the components of the design for medium to high complexity functionality.
• Be an individual contributor in the Design Tasks – RTL coding of design, synthesis, CDC analysis, debug, Test development etc.
• May need to interact with customers to discuss/ understand customers’ specification requirements, if needed .
• The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.

• Knowledge of one or more of protocols: Ethernet,  DDR, PCIe, USB, MIPI-UFS/Unipro/ SD-MMC/ /USB/AMBA (AMBA2, AXI)
• Hands on experience with architecting/ micro-architecture/ detailed design from Functional Specifications. Must have worked on control path oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design, etc.
• Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools
• Lint, CDC, Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background
• Experience with Perforce or similar revision control environment
• Knowledge of Perl/Shell scripts.
• Exposure to quality processes in the context of IP design and verification is an added advantage
• Ability to work/ Prior experience as a Technical Lead for a small team is a major plus.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.