ASIC Digital Design Engineer

Staff/Sr. Staff ASIC RTL Digital Design Engineer:

Location- Bangalore

The candidate will be part of the R&D in Solutions Group at our Bangalore Design Center, India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in a role that will include  IP Design using latest HDL and design Flows .
Job Description
The candidate will be part of the DesignWare IP Design R&D team at Synopsys. He/She will be expected to specify, design/architect and implement state-of-the-art RTL designs for the DesignWare family of synthesizable cores. He/ She will work closely with other RTL designers and be part of a global team of expert Engineers.
Job Responsibilities -

• Will be working on the next generation High Performance designs for commercial, Enterprise and Automotive applications
• Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create architecture and micro-architecture with detailed design documents for some of the components of the design for medium to high complexity functionality.
• Be an individual contributor in the Design Tasks – RTL coding of design, synthesis, CDC analysis, debug, Test development etc.
• May need to interact with customers to discuss/ understand customers’ specification requirements, if needed .
• The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide.

 Must have Bachelors/Masters degree in EE/EC/VLSI with 4+ years of relevant experience in the following areas:

• Hands on design of data path designs and algorithmic blocks such as Reed Solomon FEC encoder and Decoder as per IEEE 802.3-bj,ck,bs specifications, BCH codes, Parallel CRC computation architectures, MAC SEC engines. Experience in datapath architecture designs for area, latency, throughput trade-offs
• Knowledge of one or more of protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro/ SD-MMC/ /USB/AMBA (AMBA2, AXI)
• Experience with control path oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design, etc.
• Hands on experience with architecting/ micro-architecture/ detailed design from Functional Specifications.
• Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools
• Lint, CDC, Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background.
• Experience with high speed design greater than 600MHz and with P&R aware synthesis including usage of tools such as Fusion Compiler is a significant plus.
• Experience with Perforce or similar revision control environment
• Knowledge of Perl/Shell scripts.
• Exposure to quality processes in the context of IP design and verification is an added advantage
• Ability to work/ Prior experience as a Technical Lead for a small team is a major plus.
• Should be able to mentor and technically lead a team of designers.

In addition, the candidate should have good communication skills, should be a team player and possess good problem solving skills and show high levels of initiative.
This position requires prior industry experience and is not open for college fresh grads.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.