ASIC Digital Design , Staff Engineer

Category Engineering Hire Type Employee Job ID 18745 Remote Eligible No Date Posted 09.17.2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years building digital logic that has to actually work in silicon, not just pass simulation, actually work, at 600MHz+ clock speeds with real area budgets and power constraints that matter. You know that the difference between an IP core that ships and one that gets redesigned is usually a micro-architecture decision made during spec review, and you are the kind of engineer who catches that decision before it becomes a six-month debug cycle.

You are comfortable moving between protocol specs like PCIe Gen5 or Ethernet 400G and the actual RTL that implements them, translating pages of standards documents into data paths that close timing and control logic that handles every corner case. You do not need a perfect specification to get started. You ask the right questions, sketch out the architecture, and find a way through ambiguity without creating technical debt downstream.

You like hard problems. Reed Solomon FEC engines, MAC SEC pipelines, CDC domains that cross multiple clock regions, these are not obstacles, they are the work. You have debugged synthesis mismatches at 2am, you have rewritten a critical path to shave 200ps, and you have mentored someone through their first timing closure. At Synopsys, you will work on DesignWare IP cores that power everything from automotive SoCs to enterprise data centers. The team is global, the RTL is real, and what you build will ship in millions of devices.

What You'll Be Doing

• Architect and implement RTL designs for DesignWare IP cores targeting commercial, enterprise, and automotive applications, translating protocol specifications into detailed micro-architectures and design documentation
• Own hands-on RTL coding in synthesizable Verilog/SystemVerilog for medium to high complexity features, including data path logic like Reed Solomon FEC, BCH codes, CRC engines, and MAC SEC implementations
• Drive synthesis, static timing analysis, CDC analysis, lint checking, and P&R-aware synthesis using tools like Fusion Compiler, ensuring designs meet area, latency, and throughput targets at 600MHz+
• Collaborate with global engineering teams and engage directly with customers to refine specifications, resolve design ambiguities, and align on feature requirements
• Lead technical reviews, debug complex RTL issues across simulation and synthesis, and develop test strategies that ensure design quality and coverage
• Mentor and technically lead a team of RTL designers, providing guidance on coding practices, design trade-offs, timing closure techniques, and process improvements
• Manage design flows using version control systems like Perforce and automate repetitive tasks with Perl or Shell scripting to improve team efficiency

The Impact You Will Have

• Enable Synopsys to deliver industry-leading IP cores for Ethernet, DDR, PCIe, USB, and other high-speed protocols that power next-generation chips across automotive, enterprise, and consumer markets
• Accelerate time-to-market for customers by delivering robust, synthesizable IP that integrates cleanly and closes timing on the first pass, reducing their integration risk and schedule pressure
• Elevate the technical capabilities of your team through hands-on mentorship and leadership, building a culture where designers learn advanced techniques in timing closure, CDC handling, and protocol implementation
• Drive measurable improvements in design quality and efficiency by optimizing RTL architectures, automating flows, and establishing best practices that scale across the DesignWare IP portfolio
• Influence product roadmaps and feature priorities by working directly with customers and translating their real-world requirements into architectural decisions that shape future IP releases
• Contribute to the successful execution of complex, multi-site projects that set new performance and quality standards in the EDA and semiconductor IP industry
• Help Synopsys maintain its leadership position in IP design by delivering cores that meet the most demanding specifications for area, power, and performance in advanced process nodes

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, or a related technical field
• 4+ years of hands-on industry experience in ASIC RTL design, with a track record of delivering completed IP cores or complex digital subsystems to production
• Deep expertise in data path and control path design, including practical experience with Reed Solomon FEC, BCH codes, CRC architectures, MAC SEC engines, or similar error correction and security logic
• Strong proficiency in synthesizable Verilog/SystemVerilog coding, simulation, and design flows including lint, CDC analysis, synthesis, and static timing analysis
• Experience with high-speed design targeting 600MHz+ clock frequencies, P&R-aware synthesis techniques, and timing closure in advanced process nodes
• Familiarity with industry-standard protocols such as Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, or AMBA (AHB, AXI), and the ability to read and implement from protocol specifications
• Experience with version control systems like Perforce and scripting languages such as Perl or Shell for design automation and flow management; prior experience as a technical lead or mentor is a strong plus

Who You Are

• You can sit in a spec review with a customer, hear a vague requirement about latency tolerance, and walk out with a clear architecture sketch that addresses the real constraint without overbuilding
• You are the engineer who catches the CDC violation in code review before it gets to simulation, and you explain why it matters in a way that helps the junior designer learn, not just fix
• You are comfortable leading a technical discussion with a distributed team across Bangalore, Sunnyvale, and Taipei, keeping everyone aligned on the critical path without losing the details that matter
• You debug with discipline, you do not guess, you form hypotheses, you instrument the design, you trace signals, and you document what you find so the next person does not hit the same issue
• You have a point of view on design trade-offs, area versus latency, pipeline depth versus clock frequency, and you can articulate those trade-offs to an architect or a verification lead in two sentences without losing the nuance
• You stay current with industry trends, new protocols, emerging standards, and EDA tool capabilities, and you bring that knowledge back to your team to improve how you all work

The Team You'll Be Part Of

You will join the R&D Solutions Group at the Bangalore Design Center, as part of the DesignWare IP Design team. This team architects, develops, and delivers cutting-edge IP cores that enable Synopsys' global customers to achieve their design goals. The group is diverse, collaborative, and deeply technical, working across time zones with teams in North America, Europe, and Asia. The environment values creativity, knowledge sharing, and continuous growth, and the work directly impacts products that ship in everything from automotive SoCs to data center infrastructure.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.