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ASIC Digital Design, Staff Engineer

pin icon Bengaluru, Karnataka, India Apply Now
Category: Engineering Hire Type: Employee
Job ID 49022BR Date posted 04/30/2024
Job Description and Requirements :
Job Responsibilities:
-- Working on architecture, RTL Design of SerDes targeted for high speed protocols.
-- Verilog RTL coding.
-- Spyglass (CDC, RDC), Lint. Lint, CDC, Synthesis flow, Formal checking, etc is a must.
-- Debugging issues/failures & working on customizations.
-- Hands on experience in SerDes design & high speed protocols like, PCIe, Ethernet..

-- Experience with Perforce or similar revision control environment
-- Knowledge of Perl/Shell scripts.
-- Verification skills & languages.
-- Good communication, Team player.
-- Interaction with customers.

Further opportunities:
-- FW development, FPGA prototyping/validation.

Educational background:
-- BE/B.Tech/M.Tech OR equivalent with minimum 4-5 years industry experience.
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Synopsys Hiring Process 1. Apply. As an applicant, your resume, skills, and experience are being reviewed for consideration. 2. Phone screen. Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. 3. Interview. You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via zoom. 4. Offer. Congratulations! You have been selected as a finalist; your recruiter will reach out to propose your offer details. A written offer will soon follow. 5. Onboarding. You will be invited to complete new hire documents to ensure you are set-up and prepared for your first day. 6. Welcome. Your hiring manager, team, and an assigned buddy will help you get acclimated. Over the next few weeks, you will receive communications and engagement invitations that will help ramp you up for your future at synopsys

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