Responsibilities:

Ownership of complete physical implementation at block level & chip level. Responsible for delivering timing clean blocks/chip level that meet design targets.

DRC, LVS & IR closure. Evaluates all aspects of the physical design flow from place and route, timing, PV & IR and is able to setup these flows.

Experience in all chip level tasks (P&R, STA, PV, IR) . Work closely with the frontend design team to resolve design issues .

Requirements:

Candidates with MSEE/BSEE with 6+ years of related experience.

Possesses in depth understanding of specialization area plus working knowledge of one other related area.

Resolves issues in creative ways.

Exercises judgement in selecting methods and techniques to obtain solutions.

Executes project responsibilities from start to completion.

Contributes to moderately complex aspects of a project.

Determines and develops recommendations to solutions.

Works on team-driven or task-oriented projects.

May guide more junior peers with aspects of their job.

Networks with senior internal and external personnel in own area of expertise.

Strong knowledge on scripting using tcl, perl.