Formal Verification, Sr Staff Engineer

The Formal Verification Team is part of Synopsys EDA Group. We work with top-tier Synopsys customers to deploy high-quality Formal Verification Solutions and Flows on the cutting edge verification requirements of the industry.  The team works across the spectrum of verification challenges like Property Verification, Data Path Verification, Clock-gating Checks, Design Security, Automotive Safety etc. The team believes in fostering interest and opportunities to work in different aspects of the design verification. You will get to understand verification requirement and identify best suited application (APP) and develop a solution/flow using formal verification apps.  

Formal Verification Application Engineering, Sr Staff Engineer

Job Responsibilities

• Promote adoption of Synopsys Formal Verification Apps to new Customers by delivering presentations and demos
• Work with Customers to understand their flow requirements and map them to solutions available within Synopsys Formal Verification Apps
• Collaborate with RnD and Product marketing to develop new flows/functionalities
• Define formal verification flows and methodologies to improve customer productivity
• Develop custom scripts, create work arounds, and provide a quick solution while the features are being enhanced.
• Own the customer relationship, i.e. work with R&D and other teams to make sure customer requirements are well understood and track the development of features required by the customer
  
  

Job Requirements

• EE graduate from reputed school. Post-graduates are preferred
• 5-7 yrs. of industry experience in RTL design or verification engineers involved in deploying verification methodology using simulation-based technologies
• Exposure to assertion-based verification (in simulation) is preferred and experience with formal verification tool is desirable but not mandatory
• Managing verification responsibility for hardware designs, verification consulting experience is desirable
• Good understanding of hardware design (Verilog/VHDL) and micro-architecture.
• Exceptional understanding of Unix/Linux automation shell (bash, csh) and scripting (Tcl, Perl, Python)
• Great oral and written communication skills.
• Ability to work autonomously
• Expertise in one or more of scripting/programming languages like TCL/Python/Perl/SKILL
• Expertise in one or more areas like:
  • Formal Property Verification testbench development
  • Good understanding floating point arithmetic operations, C/C++ and IEEE math libraries
  • Understanding of Security architecture and verification
  • Automotive Safety (FuSa) verification
  • Getting closure and verification signoff with formal

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.