Layout Design, Engineer

Alternate Job Titles:

• Layout Design Engineer
• Analog Layout Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

As an ideal candidate, you are passionate about technology and innovation, eager to dive into the world of chip design and integration. You are a proactive learner, ready to adapt to rapid changes in technology and eager to contribute to cutting-edge projects. Your foundational knowledge in device physics and layout concepts equips you to tackle challenges in developing the next generation of DDR, HBM, and UCIe PHY IPs. You possess a keen eye for detail, ensuring that your work meets high-quality standards. Your ability to communicate effectively, both in writing and verbally, allows you to collaborate seamlessly with your team. You are open to learning and growing in a dynamic environment, making you a valuable asset to our team.

What You’ll Be Doing:

• Hands-on layout development for next-generation DDR, HBM, and UCIe IPs.
• Creating layout floorplans, routing, and performing physical verifications to meet quality requirements.
• Collaborating with design engineers to ensure layout designs meet performance, power, and area targets.
• Implementing layout matching techniques, ESD, latch-up, EMIR, and DFM considerations.
• Adhering to deep submicron effects and floorplan techniques in CMOS and FinFET technologies.
• Participating in design reviews and providing feedback to improve design quality and efficiency.

The Impact You Will Have:

• Contributing to the development of cutting-edge IP that powers innovations in technology.
• Ensuring high-quality layout designs that meet stringent performance and reliability standards.
• Helping accelerate the integration of advanced capabilities into SoCs, reducing time-to-market.
• Enhancing the overall efficiency and effectiveness of the design process through meticulous layout work.
• Supporting the creation of differentiated products that stand out in the market.
• Playing a crucial role in maintaining Synopsys’ leadership in technology and innovation.

What You’ll Need:

• Bachelor’s or Master’s degree in a relevant field (BTech/MTech).
• 0 to 1 year of relevant experience in layout design.
• Basic understanding of device physics and layout concepts.
• Knowledge of layout matching techniques, ESD, latch-up, EMIR, and DFM.
• Familiarity with deep submicron effects and floorplan techniques in CMOS and FinFET technologies.

Who You Are:

• Proactive and eager to learn new technologies and concepts.
• Detail-oriented with a strong focus on quality and precision.
• Effective communicator with good written and verbal skills.
• Collaborative team player who thrives in a dynamic environment.
• Adaptable and open to feedback, continuously seeking to improve.

The Team You’ll Be A Part Of:

You will be joining a dedicated team of engineers focused on developing next-generation DDR, HBM, and UCIe PHY IPs. Our team values collaboration, innovation, and excellence. We work closely with other design and verification teams to deliver high-quality IP solutions that meet our customers' needs. Together, we drive the innovations that shape the future of technology.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.