Layout Design, Principal Engineer

Category Engineering Hire Type Employee Job ID 10892 Remote Eligible No Date Posted 03/04/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, powering next generation data center, high speed connectivity, and AI/ML cloud computing. We lead in chip design, verification, and IP integration, empowering the creation of high performance silicon. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned professional with 12+ years of deep expertise in Analog and Mixed Signal Layout, particularly in high speed SerDes designs. You bring strong hands‑on experience in transistor‑level custom layout, advanced CMOS/FinFET nodes, and precision analog layout techniques used for multi‑GHz SerDes, PLL, ADC/DAC, LDO, and other AMS circuits. You excel in architecting complex floorplans, applying advanced matching techniques (common‑centroid, interdigitated), shielding/guard ring strategies, parasitic‑aware routing, and reliability‑driven design practices.

You understand SerDes protocols developed over the past decade and have strong insight into RX/TX macro architecture, PLL/clocking schemes, and high‑speed signal integrity layout considerations. You are detail oriented, self directed, collaborative, and passionate about building industry‑leading high‑performance analog and high‑speed connectivity silicon.

What You’ll Be Doing:

• Plan, estimate area/time, schedule, delegate, and execute layout tasks across multiple parallel SerDes and AMS IP programs.
 • Collaborate with cross‑functional partners (circuit, digital/FE, PD/BE, system teams, packaging, technology/foundry teams) to ensure seamless execution across the full physical design lifecycle.
 • Create and review layout documentation ensuring quality, completeness, adherence to foundry rules, and timely delivery.
 • Troubleshoot and guide the team on physical verification (DRC/LVS/PEX/EM/ESD/ERC) to achieve clean sign‑off across all IP blocks.
 • Perform device‑level and macro‑level floorplanning, placement, routing, matching‑aware layout, shielding, isolation, and parasitic optimization for high‑speed and precision analog circuits.
 • Drive the transistor‑level design and development of AMS layouts, including amplifiers, PLL blocks, high‑speed datapaths, bandgaps, bias circuits, ADC/DAC interfaces, and SerDes architectures.
 • Lead layout reviews, enforce best practices, elevate methodology, and mentor junior/mid‑senior layout engineers.
 • Support silicon bring‑up and root‑cause analysis for layout‑related issues.

The Impact You Will Have:

• You will lead layout development from early floorplan through final GDS, ensuring robust, scalable AMS and SerDes design closure.
 • You will guide complex SerDes and AMS layout integration including TX/RX macros, PLL/clocking blocks, analog front‑ends, and high‑speed signal paths.
 • You will contribute expertise in advanced nodes (2nm/3nm/5nm) and process technologies (FinFET, CMOS), enabling optimized LDE‑aware layout results.
 • You will drive the creation of high‑quality AMS layouts with strong performance, area efficiency, matching integrity, and parasitic control.
 • Your deep understanding of device physics, ESD, latch‑up, EM/IR, and reliability mechanisms will ensure robust silicon across all operating conditions.
 • Through strong debugging skills, you will ensure smooth PV closure and high‑confidence sign‑off readiness.
 • Your leadership in managing milestones, deliverables, and methodologies will directly influence program success and accelerate product roadmaps.
 • Collaboration across multidisciplinary teams will propel innovation in cutting‑edge data center, connectivity, and AI/ML‑driven silicon products.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
 • 12+ years of experience in Analog and Mixed Signal Layout, ideally with deep SerDes / AMS IP ownership.
 • Expertise in complete AMS layout flow from device placement through GDS sign‑off, including matching, shielding, guard rings, isolation, dummy insertion, and parasitic‑aware layout.
 • Deep knowledge of CMOS, FinFET, and advanced process technologies; strong understanding of LDE, process design rules, and device physics.
 • Strong proficiency with custom layout EDA tools including Synopsys Custom Compiler, Cadence Virtuoso, and foundry tech files.
 • Understanding of reliability concepts (EM, IR, ESD, LUP) and their application to high‑speed AMS circuits.
 • Strong problem‑solving, root‑cause analysis, and debugging capability with extracted views and silicon correlation.
 • Experience leading layout teams, mentoring talent, and owning major IP from concept to tapeout.
 • Familiarity with scripting (Skill/Python/Tcl) is a plus.
 • Experience delivering high‑volume production silicon is preferred.
 • Passion for continuous learning, methodology enhancement, and advancing layout excellence.

Who You Are:

• A proactive layout leader with strong communication and mentoring skills.
 • Detail oriented, systematic, and focused on delivering high‑quality outcomes.
 • Innovative and driven to advance AMS and SerDes layout methodologies.
 • Collaborative and effective across global and cross‑functional engineering environments.
 • A rigorous problem solver with strong technical depth, analytical ability, and architectural awareness.

The Team You’ll Be A Part Of:

You will join a dynamic, high‑performing AMS layout team building industry‑leading SerDes and high‑speed connectivity silicon. The team focuses on excellence, innovation, and continuous improvement while collaborating closely with circuit, system, CAD, technology, and backend groups.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.