R&D Engineering, Manager

Category Engineering Hire Type Employee Job ID 17518 Remote Eligible No Date Posted 05/19/2026

Alternate Job Titles

• R&D Engineering, Manager

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent a decade building and leading teams that turn RTL into silicon that actually works at 2nm, 3nm, and beyond. Not just tapes out, actually works, meeting PPA targets on schedule while navigating the chaos of advanced node bring-up. You know that the hardest part of physical design is not running the tools, it is making the right call when timing is bleeding, power is over budget, and the customer needs an answer by Friday. You have been that person in the room who sees the tradeoff three steps ahead and can explain it to both your team and a VP without losing the thread.

Managing a team is not about delegation for you, it is about building engineers who can solve problems you have not seen yet. You mentor through real work, not performance reviews. When someone on your team hits a wall with congestion or a tricky multi-corner scenario, you can sit down, look at the floorplan, and help them find the path forward.

You are comfortable in the weeds and in the strategy meeting. You can debug a hold violation in the morning and present a project roadmap to a customer in the afternoon. At Synopsys, you will lead the physical implementation of PVT Sensor IP across the most advanced nodes in production, working with a team that takes this work seriously and customers who depend on what you deliver.

What You'll Be Doing

• Lead end-to-end physical implementation of PVT Sensor IP digital modules from floorplanning through GDSII across 1.4nm to 7nm foundry nodes, driving timing closure, power optimization, and sign-off
• Manage and grow a team of ASIC physical design engineers, setting technical direction, reviewing work, and mentoring engineers through complex multi-corner, multi-mode closure challenges
• Work hands-on when needed, jumping into critical path analysis, congestion fixes, or tricky STA scenarios to unblock your team and keep projects moving
• Collaborate daily with front-end design, verification, and product engineering teams to align RTL quality, design constraints, and implementation strategy from the start
• Own project planning, resource allocation, and budget management for your team, balancing workload across multiple concurrent programs and node bring-ups
• Interface directly with customers to gather requirements, provide technical updates, resolve design issues, and ensure delivery meets their performance and schedule expectations
• Drive continuous improvement in design flows using Synopsys EDA tools, optimizing methodology for faster convergence, better PPA, and cleaner handoffs to sign-off

The Impact You Will Have

• Deliver PVT Sensor IP that ships in high-volume SoCs, enabling real-time temperature, voltage, and process monitoring that directly improves chip performance and reliability for end customers
• Set the technical standard for physical design implementation across advanced nodes, influencing how Synopsys builds and delivers IP at scale
• Build a team that can take on the next generation of design challenges, creating a culture where engineers grow, solve hard problems, and ship quality work
• Strengthen customer relationships by delivering on commitments, responding quickly to technical concerns, and ensuring IP quality meets production requirements
• Reduce time to closure and improve design predictability by refining flows, catching issues earlier, and sharing what works across programs
• Contribute to Synopsys IP portfolio competitiveness by ensuring every tapeout meets or exceeds PPA benchmarks and schedule commitments
• Shape IP quality and release processes, ensuring what you deliver is not just correct but maintainable and reusable across future projects

What You'll Need

• 10+ years in ASIC or IP physical design with proven delivery of complex designs at 7nm or below, including hands-on experience with floorplanning, place and route, clock tree synthesis, and timing closure
• Deep technical expertise across the full design flow from RTL to GDSII, including front-end understanding of synthesis and verification, and back-end mastery of STA, power analysis, and sign-off
• Direct experience managing and mentoring engineering teams, with a track record of developing engineers and delivering projects on time
• Strong working knowledge of Synopsys EDA tools including IC Compiler II, Fusion Compiler, PrimeTime, and StarRC, with experience optimizing tool flows for advanced nodes
• Demonstrated ability to manage project schedules, allocate resources, and handle team budgets in a multi-program environment
• Excellent communication skills, you can present technical content to customers, explain design tradeoffs to cross-functional teams, and write clear status updates that executives actually read
• Experience with IP quality processes, release workflows, or customer-facing IP delivery is a strong plus

Who You Are

• You can walk into a design review, spot the issue in a timing report or floorplan in two minutes, and guide your engineer to the fix without taking the keyboard
• When a project is slipping, you do not panic or blame, you figure out what is actually blocking progress, re-prioritize, and communicate the plan clearly to your team and stakeholders
• You care about growing your team, not just hitting milestones. You make time to review work, answer questions, and help engineers learn from mistakes instead of just fixing them
• You are comfortable saying no or pushing back when a requirement does not make sense, a schedule is unrealistic, or a design decision will create problems downstream
• You stay organized across multiple projects without losing sight of the details that matter, you know which corners are failing, which engineers need support, and which customers are waiting on updates
• You treat customer commitments seriously and follow through, even when it means working through a tough problem or having a hard conversation about what is possible

The Team You'll Be Part Of

You will be joining the PVT Sensor IP team, a group focused on developing embedded sensor IPs that monitor real-time chip conditions like temperature, voltage, and process variation. These sensors are integrated into SoCs across the industry, enabling performance optimization and lifetime health monitoring. The team works closely with cross-functional groups across Synopsys and directly with customers to deliver IP that meets the highest standards for performance, quality, and on-time readiness. As a leader, you will shape the technical direction of physical implementation, mentor engineers, and drive execution across multiple advanced node programs. The team operates out of Bangalore and Bhubaneswar.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.