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R&D Engineering, Sr Staff Engineer

pin icon Bengaluru, Karnataka, India Apply Now
Category: Engineering Hire Type:
Job ID 6588 Base Salary Range Date posted 10/01/2024

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

We are hiring visionary leaders for our next generation DDR/HBM/UCIe PHY IP’s!

Responsibilities:

  • Lead next generation DDR/HBM/UCIe IP development
  • Has leadership qualities and lead developments of new technologies while demonstrating good analysis and problem-solving skills
  • Acts as an advisor to employees to meet schedules and/or resolve problems
  • Perform in project leadership role and contributes to complex aspects of a project
  • Develop and maintain schedules, work in cross-functional settings while being proficient in design & verification

Requirements-

  • Qualification: BTech/MTech
  • Skills/Experience: 8+ years
  • Knowledge of CMOS processes and issues in deep submicron process technologies.
  • CMOS circuit design and layout methodology & flow; in-depth understanding of analog/mixed signal circuitry, familiarity with basic ESD concepts is an advantage.
  • Familiar with analog mixed-signal simulation strategies and having a good knowledge of Signal Integrity and/or Power Integrity is a plus.
  • Familiarity with ASIC design flow.
  • Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus.
  • Ability to lead projects with best product quality and efficiency.
  • Good written and verbal communication skills in interactions to lead development teams
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Synopsys Hiring Process 1. Apply. As an applicant, your resume, skills, and experience are being reviewed for consideration. 2. Phone screen. Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you and share more about the role. 3. Interview. You will be invited to meet with the hiring team to measure your qualifications for the role. Our interviews are held either in person or via zoom. 4. Offer. Congratulations! You have been selected as a finalist; your recruiter will reach out to propose your offer details. A written offer will soon follow. 5. Onboarding. You will be invited to complete new hire documents to ensure you are set-up and prepared for your first day. 6. Welcome. Your hiring manager, team, and an assigned buddy will help you get acclimated. Over the next few weeks, you will receive communications and engagement invitations that will help ramp you up for your future at synopsys

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