Senior Staff RTL Design Engineer

Category Engineering Hire Type Employee Job ID 17407 Remote Eligible Yes Date Posted 05/20/2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years designing silicon that actually ships, not just passes simulation, and you understand that the difference between a great IP and a mediocre one is often a decision made during microarchitecture, not after tape-out. You know how to look at a specification and see what is missing, what will break under load, and what will make integration painful six months from now. You are the engineer who catches those things early.

Working across RTL, synthesis, timing, and DFT does not feel like context switching to you, it feels like owning the whole problem. You have been in enough design reviews to know when an architecture is elegant and when it is just complicated, and you are not afraid to say so. You ask the right questions during bring-up, you debug with purpose, and you write code that someone else can actually maintain.

Mentorship matters to you. Not the formal kind, the everyday kind, where you help a colleague see the issue they have been stuck on or explain why a particular CDC violation actually matters. At Synopsys, you will work on UCIe, DDR, and Die-to-Die IPs that define connectivity for the next generation of chips, and the team will expect you to lead technically and lift others as you go.

What You'll Be Doing

• Own RTL design and implementation for high-performance mixed signal IP blocks including UCIe, DDR, and Die-to-Die interfaces
• Develop microarchitecture from specification, drive design reviews, and take technical ownership of assigned blocks through tape-out
• Write synthesizable Verilog and SystemVerilog, ensuring clean coding practices, reusability, and adherence to design guidelines
• Collaborate with analog designers, verification engineers, physical design teams, and validation leads to close timing, integrate blocks, and resolve cross-domain issues
• Drive synthesis, lint, CDC analysis, DFT insertion, and timing closure using industry-standard EDA tools
• Debug functional and timing failures, analyze coverage gaps, and support silicon bring-up and post-silicon validation
• Author technical documentation including microarchitecture specs, integration guides, and design rationale for internal and customer-facing use

The Impact You Will Have

• Deliver mixed signal IPs that enable next-generation connectivity, performance, and power efficiency in leading-edge semiconductor products
• Influence product roadmaps and feature sets by contributing architecture decisions that shape how customers integrate and deploy Synopsys IP
• Accelerate time to market for Synopsys customers by ensuring your blocks are robust, well-documented, and integration-ready
• Raise the technical bar across the team by mentoring engineers, reviewing designs, and sharing best practices that improve quality and velocity
• Help Synopsys maintain leadership in advanced IP by integrating emerging design methodologies and staying ahead of industry trends
• Contribute to successful tape-outs and first-silicon success, reducing respins and ensuring customer confidence in Synopsys solutions
• Shape the way AI and ML techniques are applied to digital design flows, driving efficiency and innovation across the organization

What You'll Need

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or equivalent
• 8+ years of hands-on experience in RTL design for IP, ASIC, or SoC development
• Strong proficiency in Verilog and SystemVerilog for RTL coding, with deep understanding of synthesizable constructs and coding for performance
• Solid experience with logic synthesis, static timing analysis, CDC, and DFT concepts, and familiarity with industry-standard EDA tools
• Proven ability to debug complex functional and timing issues across large, multi-block designs
• Experience with scripting in Python, TCL, or Perl to automate flows and improve productivity
• Understanding of standard protocols such as AMBA, PCIe, UCIe, or DDR is highly desirable, and participation in tape-outs and silicon bring-up is a strong plus

Who You Are

• You can walk into a design review, spot the architectural flaw that will cause integration pain later, and explain it clearly enough that the team agrees to fix it now
• You write RTL that someone else can read six months later without needing you in the room, and you care about that
• When a block fails timing or a CDC violation shows up late in the cycle, you do not panic, you methodically work the problem and communicate status without drama
• You mentor by example, not by lecture, and junior engineers seek you out because you make complex topics clear and actionable
• You stay current with industry trends, emerging protocols, and new design techniques, and you bring that knowledge back to the team in practical ways
• You thrive in collaborative environments where success depends on tight coordination across verification, physical design, and validation teams

The Team You'll Be Part Of

You will join a dynamic, high-performing engineering team at Synopsys Bangalore, focused on designing and delivering advanced mixed signal IPs for leading-edge semiconductor applications. The team prides itself on technical excellence, collaboration, and innovation, working closely with global counterparts across design, verification, and product engineering. Together, you will drive the creation of IPs that power tomorrow's connectivity and computing solutions.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.