Alternate Job Titles

• Sr Staff Application Engineer, Digital Implementation
• Sr Staff Engineer, Physical Design Solutions
• Sr Staff FAE, RTL to GDS Implementation
• Technical Application Engineer, Backend P&R (Principal Level)
• Solutions Engineer, ASIC Design Flow
• Sr StaffApplication Engineer, Fusion Compiler
• Lead Application Engineer, Advanced Node Implementation

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years building expertise in physical design, and you know that the difference between a chip that tapes out on schedule and one that slips by a quarter usually comes down to a methodology decision made during floorplanning or a timing bottleneck nobody caught until route. You do not just run tools, you understand why multi-source CTS works beautifully on one block and creates hold violations on another, and you can explain that tradeoff in a way that reshapes how a customer team approaches their next design.

Customer problems energize you. You like being the person who gets called when a design is stuck at 97% timing closure on a 3nm node and the team has exhausted their options. You dig in, isolate the issue, and come back with a solution that actually works, not a workaround that pushes the problem to signoff. Sitting with R&D to translate a customer pain point into a feature request feels as natural to you as sitting with a customer team to show them how a new Fusion Compiler capability solves the exact challenge they described last quarter.

At this level, you bring perspective. You have seen enough designs, enough nodes, and enough tool generations to spot patterns others miss. You know when a customer issue is a one-off design quirk and when it signals a methodology gap that will affect ten other customers in six months. At Synopsys, you will work on the designs that power AI accelerators, autonomous vehicles, and 5G infrastructure, and the customers you support will remember your name because you helped them ship.

What You'll Be Doing

• Deploy Fusion Compiler and ICC2 on customer designs at advanced nodes (5nm, 3nm, and beyond), solving complex PPA challenges using machine learning placement, physical synthesis, and multi-source CTS techniques
• Work directly with customers to develop, debug, and optimize RTL to GDS implementation flows, identifying design bottlenecks and tool behavior that blocks timing closure or violates power budgets
• Run competitive benchmarks to demonstrate Synopsys implementation solutions against rival tools, documenting QoR improvements and building the technical narrative that wins customer evaluations and displaces competition
• Translate customer findings into clear, actionable requirements for Synopsys R&D, driving tool enhancements that solve both immediate design challenges and long-term methodology gaps across the customer base
• Lead customer migration to new EDA tool versions by validating flows, identifying regressions, ensuring PPA gains carry through to production designs, and building confidence in adoption
• Act as the technical bridge between customers and Synopsys R&D, representing customer needs internally with credibility and representing product capabilities externally with authority
• Proactively identify recurring customer pain points across engagements and develop reusable solutions, scripts, or methodologies that scale beyond a single design or customer and influence product direction

The Impact You Will Have

• Customers tape out on schedule because the flow you debugged or methodology you built removed the bottleneck that was blocking their critical path to production
• Synopsys wins competitive evaluations because the benchmark results you generated prove measurable PPA advantage on real customer designs at the most advanced nodes
• R&D ships features that matter because the requirements you wrote were specific, grounded in actual design challenges, and tied directly to customer business outcomes
• Advanced node adoption accelerates across your customer base because the migration methodology you validated gives teams confidence to move to the next tool release without risking schedule
• Customer engineering teams adopt new Fusion Compiler capabilities faster because you showed them exactly how machine learning placement or advanced CTS solves their specific timing or congestion problem
• Synopsys product strategy improves because the customer insights you surface reveal gaps or opportunities the product team had not yet identified or prioritized
• Your customers view Synopsys as a strategic partner, not a vendor, because you consistently deliver solutions that work under pressure, on their timeline, and at their scale

What You'll Need

• 10+ years of hands-on ASIC design or application engineering experience, with deep expertise in physical implementation including placement, optimization, CTS, and routing
• Expert-level knowledge of Synopsys backend tools, specifically Fusion Compiler and ICC2, including logical and physical synthesis, timing closure techniques, macro placement, and routing at advanced nodes
• Strong working knowledge of RTL to GDS full flow, with the ability to debug issues anywhere from synthesis through signoff and articulate root cause to both customers and R&D
• Demonstrated experience working directly with customers or cross-functional engineering teams to solve complex technical problems under tight schedules and high stakes
• Deep understanding of advanced node design challenges (5nm and below) and the methodologies required to achieve timing, power, and area targets at scale
• Experience with static timing analysis tools like PrimeTime is a strong plus, as is familiarity with front-end synthesis flows in Design Compiler or Fusion Compiler
• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or equivalent practical experience

Who You Are

• You can walk into a customer war room where a design is failing timing by 500ps at 3nm, ask three diagnostic questions, and know where to start looking before anyone finishes answering
• You do not wait for perfect information to act, you work with what you have, isolate variables, and move toward a solution while others are still debating the scope of the problem
• You can translate a dense timing report into a two-sentence explanation of what is broken and what needs to change, and that explanation makes sense to both the customer lead and the R&D architect
• You are comfortable being the customer advocate in a room full of R&D engineers and the product expert in a room full of skeptical customer architects, and you do not lose credibility in either setting
• You know when to escalate and when to solve it yourself, and you have the judgment and experience to tell the difference in real time without second-guessing
• You stay current on what is changing in advanced node design and EDA methodology, not because it is required, but because you are genuinely curious about how the next generation of chips gets built and you want to be part of shaping that

The Team You'll Be Part Of

You will join the Application Engineering team in Bengaluru, working closely with Synopsys R&D, product management, and field teams globally to support customers across Asia and beyond. This team sits at the intersection of product development and customer success, and your work will directly shape both what we build and how customers use it.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.