ASIC Physical Design, Sr Staff Engineer

About Synopsys

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

Job Description:

The Digital Implementation team is seeking a highly motivated and innovative engineer who be part of the timing team working on timing flows, constraints, analysis & debug of timing issues that will enable physical design activities and will be responsible for timing STA and ETM signoff of the Mixed-Signal DDR PHY IPs in various cutting edge process technologies. As an “ASIC Physical Design Engineer, Sr. Staff”, the successful candidate will work on a variety of advanced DDR PHY developments including the latest standards in LP5x and DDR5. The position offers an excellent opportunity to work with an expert team of digital and mixed-signal engineers.

Responsibilities:

Tasks will include but not be limited to, setting up timing flows for each product line and design blocks, creating and maintaining STA and PNR timing constraints for block owners to use, reviewing foundry documents to setup correct timing derates and uncertainties for each process node, debugging and providing solutions for STA and ETM issues, improving the timing flows and methodologies, maintaining consistent timing flow in the main trunk for all project to download. 

The candidate will also work with the DFT team to help setup scan timing constraints for scan shift and scan capture and be able to run, analyze and debug and issues arising in design blocks

The candidate will be expected to work independently to find solutions to complex design implementation issues and to analyze and suggest improvements to the design methodology and design flow.

Additional tasks will include creation of views necessary timing views for SOC integration of the hard macros and also participating in next gen development of PHYs. 

Requirements

The successful candidate will have the following:

• A degree in Electrical/Electronic Engineering (or equivalent) with 10+ years of digital or physical design experience. Master’s degree is preferred.
• Excellent software and scripting skills (Perl, Tcl, Python), understanding of CAD automation methods.
• Strong understanding of timing constraints and static timing analysis, ETM generation
• A strong knowledge of DDR, LPDDR, MRDIMM protocols.
• Experience with advanced FinFET nodes, TSMC 16 nanometer or below, including low-power design techniques (ex: FinFET, 16nm, 12nm, 7nm, 5nm, 3nm).
• Experience with Synopsys tools or other equivalent tools for Synthesis, P&R, Physical verification, STA, Formal, EM/IR, DFT
• Understanding of digital logic and RTL circuit representation.
• Understanding of common design-for-test (DFT) implementation techniques.
• Understanding of signal integrity and power integrity.
• Excellent communication skills, ability to think and communicate at different levels of abstraction.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.