We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and innovative R&D Engineer with a deep understanding of semiconductor technology. You thrive in a collaborative environment, working closely with cross-functional teams to push the boundaries of what is possible. You possess a strong academic background in Electrical Engineering or Computer Engineering, ideally with a focus on Digital Design or Physical Design. Your experience with EDA tools and advanced process nodes makes you an invaluable asset to our team. You are proactive, detail-oriented, and eager to develop novel solutions in the System Technology Co-Optimization space. Your ability to identify design optimization opportunities and drive the Power-Performance-Area (PPA) optimization at the most advanced process nodes sets you apart. You are excited to work closely with Imec Research Center and its partners, enhancing collaboration and driving innovation in the semiconductor industry.

What You’ll Be Doing:

• Collaborating with Imec Research Center and its partners to drive semiconductor innovation.
• Developing methodologies and flows for new process technology definition and design prototypes using SNPS EDA tools.
• Working closely with R&D and Foundry partners to develop novel solutions in the System Technology Co-Optimization (STCO) space.
• Engaging in STCO and Pathfinding on the next generation of nodes.
• Understanding multi-die/3DIC solutions and the Digital Implementation space to drive STCO solution development.
• Identifying design optimization opportunities in silicon, package, EDA, architecture configuration, and methodology.

The Impact You Will Have:

• Driving the development of next-generation semiconductor technologies.
• Enhancing the collaboration between Synopsys and Imec Research Center.
• Contributing to the advancement of EDA technologies essential for semiconductor breakthroughs.
• Optimizing Power-Performance-Area (PPA) at the most advanced process nodes.
• Developing novel solutions in the System Technology Co-Optimization (STCO) space.
• Identifying and implementing design optimization opportunities to improve overall performance.

What You’ll Need:

• MSc/PhD degree in Electrical Engineering or Computer Engineering with 1+ years of experience in Digital Design, Physical Design, Place and Route, or 3DIC Design/Multi-Die domains.
• Strong understanding of Semiconductor Physics.
• Experience using EDA tools like SNPS Fusion Compiler, 3DIC Compiler, and Platform Architect.
• Ability to work closely with R&D and Foundry partners.
• Proficiency in developing methodologies and flows for process technology definition and design prototypes.

Who You Are:

You are a collaborative team player with strong communication skills. You are proactive, detail-oriented, and innovative, with a passion for driving technological advancements. Your ability to work effectively in a fast-paced environment and your enthusiasm for learning and development make you an ideal candidate for this role.

The Team You’ll Be A Part Of:

You will be a member of the EDAG Business Group (Design Technology), driving Power-Performance-Area (PPA) optimization at the most advanced process nodes. You will work closely with Imec Research Center and its partners, as well as Synopsys' internal engineering teams, to develop innovative solutions and enhance collaboration.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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