We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and innovative engineer, eager to push the boundaries of semiconductor technology. You have a solid understanding of advanced node processes and a knack for solving complex problems. You thrive in a collaborative environment, working closely with cross-functional teams to achieve rapid Power Performance Area (PPA) optimization at the most advance process node. And will develop methodologies and flow that help new process technology definition and design prototypes using Synopsys EDA tools.  You are a team player, working closely with R&D and Foundry partners to develop novel solutions in the System Technology co-optimization space (STCO)

What You’ll Be Doing:

• Working closely with IMEC Research Center and its partners as well as collaborating with our own teams.
• DTCO/STCO and Pathfinding on the next generation of nodes.
• Building system-level power analysis flow and system-level power models for mobile SoC to be used in DTCO/STCO exploration.
• Understanding of multi-die/3DIC solution and Digital Implementation space to drive STCO solution development.
• Effectively identify design optimization opportunities (silicon, package, EDA, architecture configuration, methodology, etc.)

The Impact You Will Have:

• Driving advancements in semiconductor technology through innovative design solutions.
• Enhancing the capabilities of EDA engines to meet the needs of advanced node processes.
• Contributing to the development of cutting-edge technologies like Gate-All-Around (GAA) and Backside Power Delivery Network (BSPDN).
• Improving the Power, Performance, and Area (PPA) of high-performance designs.
• Facilitating rapid deployment of new semiconductor technologies to customers.
• Strengthening Synopsys' position as a leader in chip design and software security.
• Effectively identify design optimization opportunities (silicon, package, EDA, architecture configuration, methodology, etc.) 

What You’ll Need:

• Ph.D. degree in Electrical Engineering or Computer Engineering
• 2 + years of experience in Digital Design, Physical Design, Place and Route, 3DIC Design/Multi-Die domains
• A strong understanding of Semiconductor Physics would be preferred.
• Experience in using EDA tools like SNPS Fusion Compiler, 3DIC Compiler

Who You Are:

• An innovative thinker capable of solving complex problems creatively.
• A collaborative team player who excels in cross-functional environments.
• Detail-oriented with a strong focus on achieving high-quality results.
• Proactive and adaptable, able to thrive in a fast-paced, dynamic setting.
• Excellent communicator with the ability to convey technical concepts clearly. 

The Team You’ll Be A Part Of:

You will be a member of the Foundry Core Engineering team, responsible for Design Technology Co-Optimization (DTCO) and rapid PPA closure using Synopsys products. This team works closely with leading foundry partners and fabless customers to develop EDA technologies for next-generation process technology. Your role will involve close collaboration with IMEC, a world-leading R&D and innovation hub for semiconductors and digital technology, to enhance the capabilities of EDA engines and drive semiconductor innovation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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