Alternate Job Titles

• Interface IP Applications Senior / Staff Engineer
• PHY IP Validation and Applications Senior / Staff Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years working at the boundary between analog circuits, digital systems, and the messy reality of silicon that does not always behave the way the simulation said it would. You understand that a PHY IP is not done when the layout tapes out, it is done when it works reliably in a customer's SoC at the corner case they did not tell you about until month three of integration. You know the difference between a validation plan that checks boxes and one that actually finds the issues that matter.

You are equally comfortable reviewing a PLL schematic with an analog designer, writing a Python script to automate a BER sweep, and explaining to a customer why their eye diagram looks marginal and what they need to change on their PCB. When design documentation is thin or contradictory, you ask the right questions, pull the relevant designers into a room, and build the validation plan from what you learn. You think in terms of what can actually be measured, not just what the spec says should be true.

You have strong opinions about what makes a good databook because you have read too many bad ones. At Synopsys, you will work on PHY IPs that power the next generation of AI infrastructure and chiplet systems, and what you document, validate, and explain to customers will determine whether those designs succeed or stall.

What You'll Be Doing

• Develop silicon validation plans for high-speed PHY IPs including UCIe, PCIe, USB, and MIPI, defining DC/AC characterization, jitter analysis, eye diagrams, BER testing, and compliance criteria across PVT corners
• Bridge analog and digital design teams with silicon validation engineers, translating circuit-level design intent and calibration sequences into executable bring-up procedures and validation scripts
• Support customer pre-sales engagements by presenting PHY IP capabilities, answering technical integration questions, and developing application notes with characterization data tailored to customer use cases
• Own PHY IP databooks from creation through maintenance, authoring electrical specifications, register maps, timing diagrams, and integration guides that reflect silicon-measured performance
• Work hands-on during silicon bring-up using oscilloscopes, BERTs, and signal integrity tools to measure PHY performance, triage anomalies, and drive root-cause analysis with design teams
• Define design-for-testability requirements early in the design cycle, advocating for observability features like loopback modes, BIST, and on-chip monitors
• Correlate pre-silicon simulation with post-silicon measurements, identify model gaps, and work with design teams to improve accuracy for future IP generations

The Impact You Will Have

• Enable faster silicon bring-up by delivering validation plans that catch real issues early with clear, measurable pass/fail criteria
• Accelerate customer design-in cycles by providing accurate datasheets and integration guides that reduce integration risk and support questions
• Improve PHY IP quality by feeding silicon learnings back into design guidelines, influencing how future IP is architected for testability
• Reduce post-silicon debug cycles by establishing clear communication between design and validation teams before bring-up begins
• Strengthen customer confidence in Synopsys PHY IP by serving as a credible technical resource in pre-sales, answering hard questions with data
• Drive adoption of Synopsys interface IP in AI infrastructure and chiplet systems by making complex PHY technology accessible for customer teams
• Contribute to IP portfolio competitiveness by ensuring databook quality, validation rigor, and customer support meet industry standards

What You'll Need

• You bring 8+ years of hands-on experience in semiconductor engineering with significant involvement in silicon validation, PHY IP characterization, or interface IP application engineering
• You have strong technical fundamentals across analog and digital domains, understanding high-speed mixed-signal PHY circuits like PLLs, SerDes, CDR, equalizers, and digital interface controllers
• You have direct bench experience with silicon bring-up and characterization of high-speed interface IPs using oscilloscopes, BERTs, and signal integrity measurement tools
• You understand at least one major high-speed interface standard in depth such as UCIe, PCIe, USB, MIPI, LPDDR, or BoW, including compliance test requirements
• You have written or significantly contributed to silicon validation plans, test procedures, characterization reports, or technical datasheets
• You are proficient with validation scripting and automation using Python, MATLAB, or equivalent for test automation and data analysis
• You hold a BS or MS in Electrical Engineering, Computer Engineering, or related discipline. Experience with die-to-die interface IPs, customer-facing roles, or advanced packaging characterization is a strong plus

Who You Are

• You can walk into a design review, ask three questions, and figure out which circuit blocks will be hard to characterize, then build a validation plan that addresses those risks
• You explain technical tradeoffs clearly to different audiences, from validation engineers to customer program managers to databook readers
• You are organized enough to manage multiple parallel workstreams from active silicon bring-up to databook updates to customer presentations without losing track
• You push back when a design handoff is incomplete or a databook specification is too vague, and you do it in a way that gets the issue fixed
• You work well across global teams, coordinating with designers, validation engineers, and customers in different time zones without needing someone to manage every handoff

The Team You'll Be Part Of

You will join the Interface IP engineering organization within Synopsys, working closely with analog and digital design teams, silicon validation engineers, and customer-facing application engineering teams. This is a highly cross-functional role with visibility across the full IP lifecycle from design through customer deployment. The team supports a portfolio of high-speed interface IPs targeting AI infrastructure, chiplet systems, and advanced SoC applications.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.