Staff Layout Design Methodology Engineer

Da Nang, Da Nang, Vietnam

Engineering

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Overview

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Date posted 05/14/2026

Category Engineering Hire Type Employee Job ID 17324 Date Posted 05/14/2026

About the Role

We are seeking a Staff Layout Design Methodology Engineer to define, develop, and advance the layout design methodologies powering our Mixed-Signal IP portfolio on cutting-edge advanced process nodes. This is a high-impact individual contributor role at the intersection of deep layout expertise, design automation, and cross-functional methodology leadership.

As a Staff engineer, you will be a technical authority — driving methodology innovations that improve layout quality, reduce design cycle time, and scale the productivity of the broader layout team. You will own the development of automation-driven flows, centralize design materials across IP families, and partner closely with AMS verification and foundry teams to stay ahead of process and tooling changes.

Key Responsibilities

Layout Methodology Development

Define, develop, and continuously improve layout design methodologies for Mixed-Signal IPs including analog, RF, memory, and high-speed interface blocks on advanced nodes (TSMC N5/N3, Samsung SF4/SF3, or equivalent).
Establish layout best practices covering device matching, shielding, symmetry, parasitic minimization, and reliability-aware layout for high-performance mixed-signal circuits.
Create and maintain a centralized methodology library — templates, parameterized cell frameworks, design rule decks, and annotated flow documentation — accessible and usable across global design teams.
Drive layout methodology reviews and enforce consistency, quality, and design rule compliance across multiple concurrent IP projects.

AI & Automation Tool Development

Explore, evaluate, and champion AI-assisted and automation-driven layout tools — including Synopsys Custom Compiler automation, PCell development, and emerging AI layout generators — to reduce manual layout effort and cycle time.
Develop scripted automation flows (Python, SKILL, Tcl) for repetitive layout tasks: array generation, guard ring insertion, via optimization, and design rule correction.
Build and document standardized automation flows for the team, ensuring reproducibility and enabling engineers at all levels to benefit from methodology advances.
Track the EDA landscape for new AI/ML-assisted layout capabilities and build evaluation frameworks to quantify productivity and quality impact before team-wide adoption.

Sign-Off Verification & Quality

Lead physical verification sign-off methodology: DRC, LVS, ERC, and PEX flows using Synopsys IC Validator (ICV) and StarRC, with deep knowledge of foundry rule decks and waiver management.
Define parasitic extraction strategies (StarRC/Quantus) and post-layout simulation correlation flows to ensure layout-induced performance degradation is identified and corrected pre-tape-out.
Own debug and resolution of complex DRC/LVS violations across IP blocks, providing systematic root-cause analysis and methodology-level fixes rather than one-off workarounds.
Partner with AMS verification teams to establish co-simulation methodologies that validate layout parasitics against circuit specifications.

Cross-Functional Technical Leadership

Serve as the go-to layout methodology expert for circuit designers, physical design engineers, and project managers across the organization.
Mentor mid-level layout engineers on advanced methodology, automation scripting, and sign-off best practices.
Contribute to IP reuse strategy by defining layout architecture and floorplan guidelines that support portability across process nodes and product variants.
Engage directly with foundry partners (TSMC, Samsung, or equivalent) on PDK updates, new design rule introductions, and DTCO opportunities relevant to mixed-signal layout.

Qualifications

Required

5–10 years of IC layout experience with a strong track record of tape-out success on advanced nodes.
Deep expertise in mixed-signal IC layout: transistor-level custom layout, analog matching techniques, shielding, and high-frequency layout considerations.
Hands-on proficiency with Synopsys EDA tools: Custom Compiler for layout, IC Validator (ICV) for DRC/LVS sign-off, and StarRC for parasitic extraction.
Demonstrated experience developing layout automation flows using Python, SKILL, or Tcl — with tangible productivity or quality outcomes.
Solid understanding of how layout decisions impact circuit performance, reliability, and manufacturability across analog, RF, and high-speed mixed-signal domains.
Experience working directly with advanced node foundry PDKs (TSMC, Samsung, or equivalent) including rule deck navigation and process-specific layout constraints.
BS or MS in Electrical Engineering, Microelectronics, or related discipline.

Preferred

Experience evaluating or deploying AI/ML-assisted layout tools or generators in a production mixed-signal environment.
Familiarity with high-speed die-to-die interface layout (SerDes PHY, UCIe, BoW) and the associated shielding, isolation, and impedance control requirements.
Background in advanced packaging co-design layout: bump assignment, RDL routing, and package-aware floorplanning for flip-chip or CoWoS designs.
Experience with Synopsys Fusion Compiler or ICC2 for digital-on-top mixed-signal integration and block-level physical implementation.
Contributions to internal methodology publications, conference papers, or foundry design enablement collaborations.

What We Offer

Competitive total compensation: base salary, equity, and performance bonus.
High-impact individual contributor role with direct influence on methodology across the full layout organization.
Access to cutting-edge Synopsys EDA tools, leading-edge foundry nodes, and advanced packaging ecosystems.
Collaborative, low-bureaucracy engineering culture that rewards deep technical expertise and automation-driven thinking.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

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Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.
Time Away

In addition to company holidays, we have ETO and FTO Programs.
Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
Retirement Plans

Save for your future with our retirement plans that vary by region and country.
Compensation

Competitive salaries.

** Benefits vary by country and region - check with your recruiter to confirm

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Hiring Journey at Synopsys

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When you apply to join us, your resume, skills, and experience are first reviewed for consideration.

Phone Screen

Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have.

Interview

Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role.

Offer

Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept!

Onboarding

There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation.

Welcome!

Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

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