ASIC Digital Design Verification, Sr Staff Engineer

Delhi, National Capital Territory of Delhi, India

Engineering

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Overview

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

The candidate will be part of the R&D in Solutions Group in India. The position offers learning and growth opportunities.
This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in a role that will include IP Design Verification using UVM based environment methodology.

Job Description:
The candidate will be part of the Synopsys CXL IP Design verification R&D team at Synopsys. You will own UVM based verification environment, which handles multiple features of IP, test plan creation, test case writing, random constraint creation, coverage closure, SVA and Release. As part of the work, you will closely work with lead and be part of a global team of experienced engineers.

Technical Expertise Needed:

BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 12+ years of experience in the following areas:

Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP.

Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI,APB,AHB) etc

Good knowledge of System Verilog.

Hands-on experience with coverage closure and writing SVA for IP/SOC.

Good simulation debugging skills.

Experience with Perforce or similar revision control environment.

Experience with Python/TCL or any scripting knowledge is an added advantage.

Job Responsibilities include -

Understand Standard Specifications, create testplan for the product and create UVM based testbench architecture. Propose and enhance the UVM architecture with unique idea for verification.
Be single point of contact with hands-on experience on all verification tasks – Testbench Creation – Testplan creation – Coverage closure – SVA – Release
Perform peer review of testbench code for continuous quality.
Own simulation debugs using DVE/Verdi, interact with Design Team and aid in debug and Verification closure.
The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide.
Lead team of engineers to perform various verification activities on IPs/Subsystems.
Anticipate problems and risks and work towards a resolution and risk mitigation plan.
Assist and mentor the team in day-to-day activities and grow the capabilities of verification team for future assignments.
Review various results and reports to provide continuous feedback to the team and improve quality of deliverables.
Report status to management and provide suggestions to resolve any issues that may impact execution.
The candidate must have excellent oratory and written communication skills in English, should be a team player and possess good problem-solving skills and show high levels of initiative.

This position requires prior industry experience and is not open for college fresh grads.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

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Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.
Time Away

In addition to company holidays, we have ETO and FTO Programs.
Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
Retirement Plans

Save for your future with our retirement plans that vary by region and country.
Compensation

Competitive salaries.

** Benefits vary by country and region - check with your recruiter to confirm

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Hiring Journey at Synopsys

Apply

When you apply to join us, your resume, skills, and experience are first reviewed for consideration.

Phone Screen

Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have.

Interview

Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role.

Offer

Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept!

Onboarding

There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation.

Welcome!

Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

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