R&D Engineering, Principal Engineer - IP Verification
Delhi, National Capital Territory of Delhi, India
Apply Now
Category: Engineering
Hire Type: Employee
Job ID 7264
Date posted 11/04/2024
- Experience : 8yrs to 15 years
- Expertise in UVM and System Verilog
Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. - Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies.
- Protocol experience: Should have experience on UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol
- Job responsibilities:
- Able to contribute to the development of the VIP
- Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective.
- Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective
- Locally should be to be "go-to" person on all technical aspects of VIP
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
Apply NowRelevant Jobs
-
R&D Engineering, Staff Engineer_ICV
Shanghai, China
Engineering
-
Analog Circuit Design Engineer
Ho Chi Minh City, Vietnam
Engineering
-
Analog Design Engr
Da Nang, Vietnam
Engineering
BROWSE JOBS
Find the open role that’s
Find the open role that’s
right for you
-
R&D Engineering, Staff Engineer_ICV
Shanghai, China
-
Analog Circuit Design Engineer
Ho Chi Minh City, Vietnam
-
Analog Design Engr
Da Nang, Vietnam
-
R&D Engineering, Engineer
Ho Chi Minh City, Vietnam
View all job opportunities here
View all job opportunities here