EDA Tooling, Release & Sign-off Engineer

We Are:

At Synopsys, we drive the innovations that shape how we live and connect. Our technology is central to the Era of Pervasive Intelligence — from self-driving cars to learning machines — and we lead in chip design, verification, and IP integration that power high-performance silicon and software.

Within our HPC Controller IP organization, the infrastructure and release team owns the EDA tooling, automation, and quality gates that build, package, verify, and release complex soft IP at scale. We make sure every product is assembled correctly, passes its release testing, and is signed off with confidence before it reaches customers.

You Are:

A motivated engineer who enjoys EDA tooling, flow automation, and owning the product release and sign-off process — with genuine enthusiasm for automation, quality, and using AI to raise engineering productivity, debug speed, and quality of results. You take ownership of getting a product packaged correctly, tested, and released on schedule. You partner naturally with design, verification, and implementation teams, communicate clearly, and let data guide your decisions. Logic-engineering know-how (synthesis, STA, and similar) is a welcome bonus rather than a prerequisite.

What You’ll Be Doing:

• Own and execute the product release process for complex soft IP: assemble and package deliverables, verify that contents and configurations are complete and correct, and produce clean release collateral.
• Run release testing and sign-off: exercise release regressions and quality gates, confirm the product is packaged correctly, and sign off deliverables before they ship to customers and downstream teams.
• Develop, run, and maintain EDA tooling, flow automation, and project infrastructure (Tcl/Python/Make-based), plus dashboards that track release status and quality.
• Debug tooling and release failures end to end:analyze logs and reports, isolate root cause, communicate status and risks clearly, and drive issues to closure with design, verification, and implementation teams.
• Apply AI to accelerate the work (e.g., triaging flow and release logs, summarizing regression and QoR trends, drafting and refactoring scripts).
• Improve documentation, packaging and sign-off criteria, and reusable collateral so releases stay consistent and repeatable across IP programs.
• Bonus: contribute to mid-end logic flows — synthesis, DFT, static checking (SpyGlass), formal equivalence, and power analysis — where it supports release readiness.

The Impact You Will Have:

• Products released on time, packaged correctly, and signed off with confidence.
• Faster, more scalable execution through stronger automation and AI-enabled analysis.
• Packaging, release, and quality-gate issues caught earlier in the cycle.
• Tighter collaboration and clearer communication across the design-to-release chain.
• Robust, implementation-ready soft IP shipped with clear collateral, checks, and sign-off.

What You’ll Need (Core):

• Working knowledge of EDA tooling and flow/automation development, typically gained through 2+ years of relevant experience or equivalent project work.
• Experience with — or strong aptitude for — product release and sign-off: packaging deliverables, running release regressions, and verifying content and quality gates.
• Good scripting skills (Tcl and/or Python) and a practical, automation-first mindset.
• Comfort with build/packaging systems, revision control (e.g., Perforce or Git), and regression/CI flows.
• Enough understanding of ASIC design and verification flows to support and debug the tooling around them.
• Ability to use AI tools effectively to accelerate debugging, summarize results, and improve scripts and flows.
• Strong written and verbal communication skills, including the ability to summarize issues, explain release status and risks, and align cross-functional teams on next steps
• BS/MS in Electrical/Computer Engineering, Computer Science, or equivalent experience.

Nice to have (Bonus):

• Hands-on logic engineering: synthesis, static timing analysis (STA), DFT, static checking (SpyGlass), formal equivalence (e.g., Formality), or power analysis.
• Hands-on with Synopsys tools such as Fusion Compiler, VC SpyGlass, or Formality.
• IP development methodologies, IP packaging, or reusable IP delivery / release collateral.
• Experience building CI/CD pipelines, regression frameworks, or reporting dashboards.

Who You Are:

• Proactive, curious, and adaptable.
• Collaborative, communicative, and ethical.
• Flow-oriented, AI-aware, and quality focused.
• Resilient and results oriented.

The Team You’ll Be A Part Of:

You’ll work with a high-impact High-Performance-Compute team focused on delivering complex IP to the marketplace. You will collaborate across RTL design, verification, DFT, physical design, methodology, and project infrastructure teams to improve mid-end readiness and enable predictable downstream implementation.