Analog Design, Principal Engineer

• Review SerDes standards to develop novel transceiver architectures and sub-block specifications.
• Investigate and develop circuit architectures that address architectural bottlenecks and lead to revolutionary improvements in power, area and performance targets.
• Work across project and department teams to streamline design and verification strategies ensure overall design quality, efficiency and performance.
• Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
• Present & review simulation data from internal project teams.  Present results externally at industry panels or at customer reviews.
• Document design features and test plans.
• Consult on the overall electrical characterization of the SerDes IP product.  Analyze customer silicon data for design enhancements.  Propose solutions for post-silicon design updates.

• PhD with 10+ years, or MSc with 12+ years of practical analog IC design experience; degree in Electrical Engineering or Computer Engineering or other relevant field of study.
• Experience with FinFET technologies
• Extensive design experience with sub-circuits relevant to SerDes: 
  • Receive equalizers such as CTLE, DFE, FFE
  • DAC Based transmitters and ADC based receivers, DSP equalization
  • High speed clocking circuits such as PLL, VCO, ILO, DLL and phase interpolator
  • ADC and DAC
  • Duty Cycle Correction, Clock Phase Correction Circuits
  • Digitally Assisted Analog Calibration Loops
• In depth familiarity with transistor level circuit design - sound CMOS design fundamentals, experience with CMOS tape-outs
• Knowledge of SerDes, circuit and fabrication issues that directly impact customer use-cases.
• Aware of ESD issues (i.e. circuit techniques, layout).
• Familiarity with custom digital design (i.e. high-speed logic paths, Serializer, De-serializer).
• Experience with analog/digital interactions for optimizing circuit performance (calibration, adaptation, timing-handoff, etc)
• Knowledge of design for reliability (i.e. EM, IR, aging, self heating, etc.) and layout effects (i.e. matching, reliability, proximity effects, etc.).
• Experience with tools for schematic entry, physical layout, and design verification.
• Knowledge of SPICE simulators and simulation methods.
• Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
• Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desired.
• Excellent communication, presentation, and documentation skills

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.