We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned engineering professional with a robust background in the full flow place and route processes, and you thrive in environments where you can drive technical engagement and lead innovative projects You have a proven track record of working independently on significantly complex projects, and your expertise is sought after within and outside your immediate team You possess a deep understanding of the latest technologies in design infrastructure, particularly within IPG deployment, and you are passionate about pushing the boundaries of what is possible in chip design and verification Your ability to communicate complex ideas effectively and influence stakeholders is one of your strongest assets You are adaptable, a lifelong learner, and someone who excels in a collaborative yet challenging environment

What You’ll Be Doing:

• Leading the technical engagement for full flow synthesis throughplace and route processes (RTL to GDSII)
• Collaborating with teams to drive best-in-class design infrastructure deployment
• Developing and implementing innovative solutions for physical IP design such as SERDES, DDR, and Memory
• Providing technical and engineering insight to enhance product usability and adoption
• Defining and developing ASIC RTL design and verification flowsat both chip and block levels
• Applying CAD software engineering methods to optimize design processes

The Impact You Will Have:

• Advance Synopsys' leadership in chip design
• Improve design infrastructure efficiency and performance
• Enhance integration and deployment of new technologies

• Set industry standards for physical IP design
• Improve product usability and customer satisfaction

What You’ll Need:

• Extensive experience with full flow synthesis andplace and route processes (RTL to GDSII)
• Proven track record in driving technical engagement and leading complex projects
• Strong background in ASIC RTL design and verification
• Proficiency in CAD software engineering methods

Who You Are:

You work independently with minimal supervision. You are an expert in your field, adept at addressing complex issues. You communicate effectively with stakeholders and have a significant impact on your organization. You are adaptable, innovative, and eager to learn

The Team You’ll Be A Part Of

Join a dynamic team focused on driving product proliferation and collaborating to deploy the latest technologies. We aim for excellence and push boundaries to deliver top-quality products.

Rewards and Benefits:

At Synopsys, we offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process

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