ASIC Physical Design, Sr Director in HCMC/ Da Nang

Category Engineering Hire Type Employee Job ID 16846 Remote Eligible No Date Posted 04/08/2026

Alternate Job Titles:

• Senior Director, Physical Design
• Sr Director, ASIC Digital Implementation

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a visionary leader and technical expert with a deep passion for shaping the future of AI silicon through advanced physical design. With a proven track record in high-frequency chip design, you thrive in fast-paced environments where innovation, collaboration, and technical excellence are paramount. You have mastered the intricacies of physical design flows, from floorplanning and synthesis to tape-out, and possess a nuanced understanding of the challenges posed by high-speed die-to-die interconnects and advanced process nodes.

 You are adept at leading globally distributed teams, uniting diverse talents and perspectives across geographies. You foster a culture of inclusivity, accountability, and growth, mentoring engineers at all levels while driving organizational excellence. Your communication skills enable you to bridge technical and business domains, ensuring alignment with strategic objectives and seamless execution of complex projects.

 You are energized by the opportunity to define methodologies, adopt new technologies, and champion automation and innovation. You’re comfortable navigating ambiguity and thrive on solving complex engineering problems, leveraging your expertise in both technical strategy and people leadership. You value collaboration, cross-functional partnerships, and are relentless in your pursuit of delivering high-quality silicon that powers the next generation of AI infrastructure. Your commitment to continuous learning and improvement makes you a respected leader and trusted advisor within the organization.

What You’ll Be Doing:

• Owning and driving the end-to-end physical design flow for high-speed die-to-die interconnect and interface chips targeting 2 GHz+ on advanced process nodes (sub-7nm/5nm/3nm).
• Leading floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification with emphasis on die-to-die interface placement and bump/pad ring constraints.
• Achieving timing closure across all corners and modes, with expertise in multi-corner multi-mode sign-off for high-speed serial and parallel interfaces.
• Driving power integrity, signal integrity, and thermal analysis to meet stringent tape-out criteria for high-bandwidth die-to-die links.
• Defining and owning physical design methodology, Synopsys tool flows, and best practices across the organization.
• Building, mentoring, and leading a globally distributed team, establishing effective communication and collaboration norms to foster cohesion and engineering excellence.
• Collaborating cross-functionally with RTL design, DV, architecture, CAD/EDA, and program management teams globally.
• Owning physical design schedules and milestones for multiple concurrent projects, communicating status to senior leadership and mitigating risks proactively.
• Championing automation and scripting to improve PPA outcomes and team productivity.

The Impact You Will Have:

• Enable the physical implementation of high-speed die-to-die interconnects that power large-scale AI accelerators, GPU clusters, and multi-die systems.
• Deliver ultra-low latency, high-bandwidth chip-to-chip communication at the core of next-generation AI infrastructure.
• Advance the adoption of cutting-edge process nodes and interface standards, positioning Synopsys as a leader in silicon innovation.
• Ensure robust engineering quality, execution velocity, and successful tape-outs across global teams.
• Drive organizational excellence by fostering a culture of accountability, growth, and technical mastery.
• Shape methodologies and tool flows that set industry benchmarks for high-speed, advanced-node physical design.
• Contribute to the strategic direction of AI silicon and interconnect products, impacting the broader technology ecosystem.

What You’ll Need:

• 15+ years of hands-on physical design experience, with deep expertise in high-frequency (≥2 GHz) chip design.
• Expertise with Synopsys IC Compiler II (ICC2), PrimeTime, Fusion Compiler, StarRC, IC Validator, and PrimePower.
• Track record of taping out high-speed interface ICs, die-to-die interconnect chips, SerDes, or similar designs at advanced process nodes (7nm, 5nm, 3nm).
• Understanding of die-to-die interface standards and protocols (UCIe, BoW, HBI, XSR, or proprietary) and their physical implementation.
• Experience with power intent flows (UPF/CPF), low-power design techniques, and dynamic/static power optimization.
• Strong scripting skills (Tcl, Python, Perl) for tool flow automation and PPA optimization.
• Proven ability to lead and grow globally distributed engineering teams of 10+ people.
• Cross-cultural communication and collaboration skills; experience working across US, Asia, or European engineering centers.
• BS or MS in Electrical Engineering, Computer Engineering, or related field (PhD preferred).

Who You Are:

• Inspirational leader with a collaborative and inclusive approach.
• Strategic thinker with a passion for innovation and continuous improvement.
• Excellent communicator, able to translate complex technical concepts for diverse audiences.
• Resilient and adaptable, thriving in fast-paced and ambiguous environments.
• Mentor and coach, dedicated to developing talent and fostering teamwork.
• Detail-oriented and accountable, with a strong sense of ownership.

The Team You’ll Be A Part Of:

You will join a globally distributed Silicon Engineering team focused on the physical implementation of cutting-edge AI silicon and high-speed die-to-die interconnects. Our team spans multiple sites and time zones, collaborating with process technology, packaging, RTL, DV, architecture, CAD/EDA, and program management teams. We pride ourselves on a culture of technical depth, low bureaucracy, and a relentless drive for engineering excellence.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.