Design Verification Senior/Staff Engineer

Job Overview

We’re looking for Design VerificationSenior/Staff Engineerfor working on ASIC/SOC projects, at Synopsys Ho Chi Minh City, District 7.

Responsibilities and Duties

• Design Verification

SNPS SSG team are leading to provide the solutions of many kinds of sub-systems integrated of latest communication protocols (USB, DPTX, PCIe/CXL, DDR ...). Our DV team cooperates directly with US site to proceed verification for these subsystems. We are continuously updating the latest technologies related communication protocols and verification methodology.

Join with us, you can directly work with US site expert, up to date your knowledge of Design Verification.

Qualifications

• 5-8 years of experience in ASIC verification
• Knowledge of ASIC design and verification flow from specifications to final drop of RTL
• Knowledge of UNIX environment, Perl, Shell scripting, Verilog/System Verilog language, testbench development
• Knowledge of verification tools of Synopsys (VCS, Verdi, DVE ...)
• Good written and oral communication skills in English
• Knowledge of verification methodology such as UVM and/or Formal Verification is a plus
• Knowledge of USB, DPTX, DDR, PCIe, SATA, MIPI is a big plus
• Knowledge of Gate Level simulation is a plus

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.