Senior Design Verification Engineer in Tan Binh district

Alternate Job Titles:

• ASIC Verification Senior Engineer
• Senior Digital Design Verification Engineer
• Senior ASIC Design Verification Specialist

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a talented and driven ASIC Design Verification Engineer with a passion for developing high-speed mixed-signal PHY IPs. You have a solid background in front-end ASIC development flows, including RTL verification, GLS verification, VCD generation, and power generation using PrimeTimePX. You thrive in a collaborative environment and possess excellent communication skills, enabling you to effectively work with teams across the globe. You are looking for an opportunity to be trained and developed by experts from around the world while contributing to innovative projects in a professional, fair, and fun working environment. You are motivated by the prospect of a clear career path, with opportunities to advance either as a Technical Professional or Design Manager.

What You’ll Be Doing:

• Working in a Digital design team to develop high-speed mixed-signal PHY IPs
• Participating in RTL/GLS verification for mixed signal PHY IP
• Developing and executing functional test/verification plans
• Performing RTL and gate-level SDF-annotated simulations, UVM based environments
• Generating VCD files and power reports using PrimeTime PX
• Communicating and collaborating with cross-functional teams globally

The Impact You Will Have:

• Enhancing the performance and reliability of high-speed mixed-signal PHY IPs
• Contributing to the development of cutting-edge technologies in the semiconductor industry
• Ensuring the successful verification and validation of ASIC designs
• Improving the efficiency and effectiveness of the design verification process
• Supporting the continuous innovation and advancement of Synopsys' product offerings
• Driving the success of cross-functional projects through effective communication and collaboration

What You’ll Need:

• At least 2 years of experience in ASIC RTL design flow
• Proficiency in RTL and GLS verification and debugging
• Experience with high-speed interface protocols (DDRPHY, HBM PHY, PCIe PHY) is a plus
• Knowledge of SystemVerilog and UVM is a plus
• Excellent teamwork and communication skills in English

Who You Are:

• A highly motivated and detail-oriented individual
• An effective communicator with strong collaboration skills
• A problem solver with the ability to analyze and resolve complex issues
• A continuous learner who stays updated with the latest industry trends and technologies
• A proactive contributor who takes initiative and delivers results

The Team You’ll Be A Part Of:

You will be part of a dynamic Digital design team focused on developing high-speed mixed-signal PHY IPs. Our team is composed of talented engineers who are dedicated to innovation, excellence, and collaboration. We work in a supportive and inclusive environment where your contributions will be valued and recognized.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.