We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced 3DIC and Advanced Packaging Physical Implementation Engineer with a strong background in backend design, particularly in deep sub-micron technology. You have a proven track record of RTL to GDS tape out for advanced technology nodes and possess excellent electronic skills. Your can-do attitude and quick learning abilities make you a valuable team player in a global and highly skilled team. You thrive in a collaborative environment, are adept at problem-solving, and have a keen eye for detail. Your communication skills are exceptional, enabling you to interface effectively with various teams and customers.

What You’ll Be Doing:

• Performing 3DIC design partition, floor planning, IP placement, TSV placement, and power grid planning and design.
• Optimizing for power and thermal performance.
• Generating 3D stacking, hybrid bonding pad, and ubump map.
• Designing AP RDL and performing Place and Route.
• Conducting EMIR analysis, DRC, and LVS.
• Designing silicon interposer and silicon bridge.
• Generating GDS and managing the tape out process.
• Creating design guidelines and best practices.
• Providing IP and chiplet pre-sales P&R mockup design and post-sales support.
• Interfacing with Synopsys EDA tool and internal CAD group to build 3DIC and 2.5D design flow.
• Collaborating with the IP implementation group to develop different views and enable the design flow.

The Impact You Will Have:

• Driving innovation in 3DIC and advanced packaging technologies.

• Enhancing power and thermal efficiency in chip designs.
• Contributing to the successful implementation of Synopsys IP, test chips, and chiplets.
• Improving design flows and methodologies for advanced technology nodes.
• Supporting customers in exploring and optimizing their solution space.
• Enabling the seamless integration of Synopsys tools and technologies in customer projects.

What You’ll Need:

• Minimum of 10+ years of relevant experience in physical design
• Deep sub-micron technology large scale chip tape out experience from RTL to GDS.
• Domain expertise in placement and route tools such as Fusion Compiler and Innovus.
• Proficiency in EMIR analysis and DRC/LVS tools.
• Knowledge of 3DIC and 2.5D advanced packaging, silicon interposer, and bridge.
• Experience in power analysis and Custom Compiler is a plus.

Who You Are:

• A strong communicator and team player.
• Capable of working independently with minimal supervision.
• Adept at handling significant and unique issues requiring complex evaluation.
• Effective in communicating with both internal and external stakeholders.
• Possessing extensive expertise and a commitment to contributing to organizational objectives.

The Team You’ll Be A Part Of:

You will be part of a global, highly skilled, and supportive team focused on driving advancements in 3DIC and advanced packaging technologies. Our team collaborates closely with various departments to develop innovative solutions and optimize design flows, ensuring the successful implementation of Synopsys tools and technologies in customer projects.