ASIC Digital Design Engineer, Sr. Engineer

Job Description:
The selected candidate will be a supervised contributor of Synopsys DesignWare Processor team involving in development of leading edge DesignWare processor IP products such as HPC processors, NN accelerators, vision processors, as well as energy-efficient processors.
 The responsibility is to complete assignments meeting quality of result targets under appropriate supervision. The assignments could be applied to architecture, micro-architecture, performance analysis, logic design, verification and validation operations, as well as related engineering flows or environments and necessary signoff delivery processes. Depending on individual’s capability and career development, the works may include but not limited to investigation, creation, implementation, analysis, debugging, and optimization in said areas. In addition, the candidate would have great opportunities to collaborate with cross-team or cross-site colleagues on various technical matters such as algorithms, methodologies, quality of delivery, SoC prototyping, system bring-up, or any other engineering works that are required for overall business operations.

Job Requirements:

• Master degree in EE or CS related engineering major is required as a minimum from a reputed college
• Minimum 0-3 years of experience in digital frontend design or verification
• Basic knowledge in microprocessor architecture, memory architecture, and system architecture
• Basic hands-on experiences in architecture, micro-architecture and RTL design, or functional and performance modeling, performance profiling, performance benchmarking, or simulation verification based on UVM with co-simulation, functional formal, functional coverage, regression flows/environments and respective debugging activities
• Programming skills: SystemVerilog, SystemVerilog Assertion, Verilog, C/C++, assembly, Perl, Python, or shell scripts
• Tools: RTL linters, simulators, synthesizers, functional formal, functional coverage, team work tools (continuous integration, source control management, issue tracking, etc.), ADL-based generation tools (such as Synopsys ASIP Designer), or software toolchains
• Experience in multi-site collaboration is a plus
• Written and Verbal communication skills:
  1. Creation, modification and review of documentation: design or verification work plans, engineering quality processes, test scenarios, test reports
  2. Ability to profile the values, requirements, issues, risks, and solutions for engineering works presentation and persuade and compromise for consensus
  3. Ability to follow disciplines describing issues and changes in track systems
• Self-motivated team player; be able to thrive in a fast-paced engineering environment

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.