ASIC Digital Design, Sr Manager

Job Description
The selected candidate will be an engineering manager with technical leadership co-role of the Synopsys DesignWare Processor team in Hsinchu and involved in the development of leading edge DesignWare processor IP products such as NN accelerators, vision processors, as well as high-performance or energy-efficient general purpose processors. The management responsibility is to continuously grow the local R&D team according to overall development strategies, to ensure highly engagement and motivated of the team members, to coordinate professional development and career advancement for team members, as well as to participate in overall operation planning and tracking. In the technical leadership co-role this person is expected to take significant ownership and accountability on quality of delivery for at least a block of design and/or verification functions within a product development effort, and to be capable of acting a project manager role in project execution. Specifically, this should cover but not limited to the authorship of plans and specs for the owned functions, guiding, coaching, and tracking for appropriate execution with necessary leadership and hands-on works, as well as escalating the overall team capability. The hands-on works could cover architecture analysis, micro-architecture, logic design and implementation, formal verification, simulation verification, as well as related engineering flows and environments and necessary signoff and delivery processes, depending on individual’s capability and career development, which would include but not limited to related creation, implementation, analysis, debugging, and optimization work. In addition, the candidate would have a great opportunity to collaborate cross-team and cross-site in management and technical-oriented matters such as product roadmap profiling, project initiation, customer satisfaction, algorithm analysis, methodology development, quality improvement, product delivery, or SoC
implementation and system bring-up, or any other engineering works that could be needed for the overall ARC team business.

Job Requirements:
• Master degree in EE or CS related engineering major is required as a minimum from a reputed college
• Minimum 15 years of experience in related digital frontend design or verification for IP business, with 8 years in technical leadership or engineering management roles
• Proven leadership and ownership experience with solid quality of delivery and escalation of overall team capability.
• Comprehensive knowledge in microprocessor architecture, memory architecture, and system architecture • HDL and Verification languages: SystemVerilog, Verilog • In-depth hands-on experiences in micro-architecture and RTL design, or verification methodologies such as UVM/OVM, functional formal, functional coverage, with authorship of technical specs
• Programming skills: SystemVerilog, C/C++, assembly, Perl, Python, scripts
• Tools: RTL linters, simulators, synthesizers, functional formal, functional coverage, team work tools (continuous integration, source control management, issue tracking, etc.), ADL-based generation tools (such as Synopsys ASIP Designer)
• Experience with multi-site development is essential
• Project management skills: requirement profiling, resource, work, and schedule planning and tracking, risk and quality assessment and management, as well as justification on execution objective, strategy, value proposition, and ROI evaluation • Written and Verbal communication skills: o Creation, modification and review of documentation: design or verification work plans, engineering quality processes, test scenarios, test reports
o Ability to profile the values, requirements, issues, risks, and solutions for engineering works presentation and persuade and compromise for consensus o Ability to follow disciplines describing issues and changes in track systems
• Analytical skills: o Analysis of signoff requirements for product releases o Ability to analyze QoR and verification results for major milestone reviews and assessments.
• Self-motivated team player with leadership, be able to thrive in a fast-paced engineering environment
• Ability to guide, coach, motivate, and influence team members toward desired results

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.