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Design Verification Applications Engineer, Sr Staff to Principal

pin icon Hsinchu, Taiwan Apply Now
Category Engineering Hire Type Employee Job ID 17056 Date posted 04/21/2026

Alternate Job Titles

  • Principal Verification Applications Engineer
  • Sr Staff Applications Engineer, Design Verification
  • Principal Field Applications Engineer, Verification
  • Staff to Principal Applications Engineer, DV
  • Principal Technical Solutions Engineer, Verification

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.


You Are

You have spent years deep in verification, building and debugging SystemVerilog and UVM testbenches that actually close coverage on complex SoCs, not toy examples. The difference between a testbench that finds bugs and one that just runs is something you see immediately, and you know how to fix it without rewriting the whole thing. You think in constraints, assertions, and coverage bins, and you have learned that the hardest part of verification is not writing the code, it is getting a team to adopt the methodology and trust it enough to sign off.

Working across cultures and time zones does not slow you down. You can sit with a customer engineer in Hsinchu, diagnose a UVM sequencer issue in real time, and walk out with a plan that unblocks their regression by end of week. You do not wait for perfect documentation, you dig into the problem, script a workaround if needed, and follow up with a clear write-up that helps the next person avoid the same trap.

You care about the customer outcome, not just the tool feature. At Synopsys, you will work with semiconductor teams building the chips that power everything, and what you enable will directly affect their ability to tape out on time.

What You'll Be Doing

  • Drive adoption of Synopsys Verification solutions at leading semiconductor companies across Taiwan and Asia, working directly with customer engineering teams on live SoC projects
  • Debug and optimize SystemVerilog and UVM testbenches, helping customers resolve coverage gaps, assertion failures, and regression bottlenecks that block sign-off
  • Deliver technical workshops, training sessions, and hands-on demos that get customer teams up to speed on constrained random verification, coverage closure, and SoC-level methodology
  • Collaborate with Synopsys R&D teams to relay real customer use cases, tool gaps, and enhancement requests that shape the next product release
  • Author technical documentation, application notes, and internal knowledge base articles that capture best practices and repeatable solutions
  • Support SoC-level regression and coverage closure activities, working alongside customer teams to help them hit verification milestones and tape-out deadlines
  • Interface with sales, support, and field teams to ensure technical issues are resolved quickly and customers stay confident in their toolchain


The Impact You Will Have

  • Enable customers to adopt advanced verification methodologies faster, directly reducing their time from RTL freeze to tape-out
  • Improve customer satisfaction and tool confidence by delivering timely, high-quality technical solutions that unblock critical project milestones
  • Accelerate verification cycles by helping customers implement coverage-driven and constrained random flows that catch more bugs earlier
  • Influence Synopsys product direction by feeding real-world customer feedback and use cases back to R&D, shaping tools that work better in production
  • Help customers achieve higher coverage closure rates and verification sign-off quality, contributing to the success of high-performance silicon products that ship to market
  • Build a culture of technical excellence and knowledge sharing within the customer community and across Synopsys field teams
  • Strengthen Synopsys market leadership in verification by turning successful customer engagements into long-term partnerships and advocacy


What You'll Need

  • Bachelor's or Master's degree in Electrical Engineering, Computer Science, or equivalent hands-on experience in verification engineering
  • Extensive experience building, debugging, and optimizing SystemVerilog testbenches, SystemVerilog Assertions, and UVM-based verification environments
  • Proven track record with constrained random verification, coverage-driven verification, SoC-level regressions, and coverage closure on real production projects
  • Strong scripting skills in Perl, Python, Tcl, Bash, or Makefile for automation, tool integration, and workflow optimization
  • Demonstrated ability to diagnose and resolve complex verification issues in large, multi-block SoC environments
  • Excellent technical writing skills in English, especially for specifications, application notes, and customer-facing documentation
  • Fluency in written and spoken English, experience working with global teams and customers is a strong plus


Who You Are

  • You can walk into a customer meeting, listen to a vague description of a UVM issue, ask three clarifying questions, and leave with a concrete action plan
  • You are comfortable presenting technical content to a room full of engineers and adjusting your explanation based on who is nodding and who is not
  • You stay organized across multiple customer engagements, tool versions, and open issues without losing track of what needs to close this week
  • You adapt quickly when a customer throws you a curveball, a new tool version, a different flow, a legacy codebase, and you find a way to make it work
  • You are genuinely curious about new verification techniques, EDA tools, and automation approaches, and you bring that energy into customer conversations
  • You thrive in a cross-functional, multicultural environment where collaboration and clear communication make the difference between a stuck project and a successful tape-out


The Team You'll Be Part Of

You will join a high-impact Applications Engineering team based in Hsinchu, Taiwan, focused on enabling success for leading semiconductor and system companies across Asia. The team is passionate about driving customer adoption of Synopsys Verification solutions, collaborating closely with R&D, sales, and support teams to deliver exceptional results. You'll find a culture of innovation, mentorship, and continuous learning, where your contributions will be valued and your professional growth supported.


Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Apply Now

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