Alternate Job Titles

• Staff Verification Applications Engineer
• Senior Technical Applications Engineer, RTL Verification
• Staff Field Applications Engineer, Design Verification
• Technical Lead, Verification Solutions
• Staff Applications Engineer, Timing and Verification

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent a decade in the trenches of digital design, where timing exceptions are not theoretical exercises but the difference between a chip that tapes out and one that doesn't. You know what it looks like when a customer's constraint deck has 3,000 false paths and half of them are wrong, and you know how to walk them back from that edge without making them feel like they've been doing it wrong for years.

You are comfortable sitting with a design team in Hsinchu on Tuesday debugging why their CDC violations won't converge, then jumping on a call with R&D in Mountain View on Wednesday to explain exactly what the tool needs to do differently. You translate between what the tool can do and what the customer actually needs, and you do it without losing either side.

Methodology deployment is your craft. You have built flows that teams actually use, not ones that look good in a slide deck. You script in Tcl and Python because you have to, not because you love it, and you have debugged enough PrimeTime correlation issues to know that the problem is usually three layers deeper than where it first appears. At Synopsys, you will work with Taiwan's most strategic semiconductor accounts on verification and timing solutions that determine whether their next-generation SoCs actually work.

What You'll Be Doing

• Lead full-cycle deployments of Timing Constraints Management (TCM), VC SpyGlass, and VCS across strategic accounts, from evaluation through production adoption and methodology integration
• Debug complex timing constraint issues including false path validation, multi-cycle path analysis, clock-domain crossing verification, and STA-to-simulation correlation problems in real customer designs
• Drive pilot projects that prove out constraint verification, RTL quality checking, and simulation-based timing validation flows in advanced-node SoC environments
• Build automation scripts and reusable deployment methodologies in Tcl, Python, and Perl that improve customer productivity and reduce time to signoff
• Deliver technical workshops and hands-on training on TCM constraint management, VC SpyGlass lint/CDC/RDC flows, and VCS simulation debug techniques
• Collaborate directly with R&D teams to escalate critical customer issues, validate new features, and shape product roadmaps based on what you see in the field
• Partner with sales and product management to identify technical expansion opportunities within accounts and translate customer pain points into business growth

The Impact You Will Have

• Enable Taiwan semiconductor leaders to close timing on complex SoCs faster by deploying constraint verification methodologies that catch errors before they reach signoff
• Reduce customer debug cycles by building simulation and formal flows that correlate cleanly with static timing analysis, eliminating weeks of back-and-forth
• Drive adoption of VC SpyGlass across RTL verification teams, improving design quality and reducing CDC/RDC violations that would otherwise escape to silicon
• Shape how Synopsys verification tools evolve by feeding real customer use cases and methodology gaps directly back to product development
• Accelerate time-to-production for strategic accounts by creating reusable deployment frameworks that scale across multiple design teams and projects
• Build long-term technical relationships with customer architects and methodology leads, becoming the trusted advisor they call when a critical project is at risk
• Expand Synopsys footprint in key accounts by proving technical value in one domain and opening doors to adjacent tool adoption

What You'll Need

• MS in Electrical Engineering, Computer Engineering, or equivalent technical discipline
• 10+ years of hands-on experience in digital design implementation, static timing analysis, RTL verification, or signoff methodologies in a production environment
• Deep working knowledge of SDC constraints, timing exceptions, false path and multi-cycle path analysis, clock-domain crossing, and timing closure flows
• Proven experience debugging timing correlation issues between simulation-based validation and STA tools like PrimeTime or Tempus
• Strong technical background in lint, CDC, RDC, and structural verification methodologies, ideally with tools like VC SpyGlass or equivalent
• Proficiency scripting in Tcl, Python, Perl, or shell for automation, flow development, and customer-specific methodology customization
• Experience supporting advanced-node SoC or ASIC designs is a strong plus, familiarity with enterprise-scale verification deployment across multiple teams is valuable

Who You Are

• You can walk into a war room where a customer's timing closure is stuck and within an hour identify whether the problem is a constraint issue, a tool setup issue, or a fundamental methodology gap
• You explain complex tradeoffs to customer architects in two sentences without losing the nuance, and you know when to simplify and when to go deep
• You manage multiple customer engagements simultaneously without dropping threads, keeping internal teams aligned and customers confident that their issues are moving forward
• You push back when a deployment plan is missing critical steps or when a customer is headed toward a methodology dead-end, and you do it in a way that builds trust rather than friction
• You are comfortable with ambiguity, working from incomplete design data, evolving requirements, and customer environments where the documentation is six months out of date
• You treat customer success as your success, not because it's in a mission statement but because you know that a clean tapeout using your methodology is what actually matters

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.