ASIC DFT, Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a driven and detail-oriented individual with a passion for cutting-edge technology and continuous learning. With 0-1 years of related experience, you possess a sufficient understanding of DFT architectures and methodologies, including Scan insertion, ATPG, JTAG, and SIMS. You have moderate experience in generating scan patterns and coverage statistics for various fault models like stuck-at, IDDQ, transition faults, and path delay. Your experience in scan stuck-at and at-speed coverage exploration, simulation, and debug is commendable. Familiarity with state-of-the-art EDA tools for DFT, design, and verification is a plus. Additionally, you have some knowledge of STA for DFT mode timing constraint development and exploration. Your debugging skills and demonstrated experiences in Perl/TCL/Python scripting are an advantage. You are an excellent communicator and can effectively work with cross-functional teams across geographies. Design experience in MBIST, LBIST, and Analog DFT is an added advantage. You value inclusion and diversity and are committed to contributing to a collaborative and innovative work environment.

What You’ll Be Doing:

• Implementing DFT architectures and methodologies, including Scan insertion, ATPG, JTAG, and SIMS.
• Generating scan patterns and coverage statistics for various fault models.
• Exploring, simulating, and debugging scan stuck-at and at-speed coverage.
• Utilizing state-of-the-art EDA tools for DFT, design, and verification.
• Developing and exploring STA for DFT mode timing constraints.
• Collaborating with cross-functional teams across geographies to achieve project goals.

The Impact You Will Have:

• Enhancing the reliability and quality of our high-performance silicon chips through robust DFT methodologies.
• Contributing to the efficiency of our chip design and verification processes.
• Supporting the continuous innovation of our technology and products.
• Ensuring seamless integration of DFT in our chip design workflows.
• Improving fault detection and coverage, thereby reducing time-to-market for our products.
• Fostering a collaborative and inclusive work environment that drives technological advancements.

What You’ll Need:

• 0-3 years of related experience in DFT architectures and methodologies.
• Moderate experience in generating scan patterns and coverage statistics for various fault models.
• Experience in scan stuck-at and at-speed coverage exploration, simulation, and debug.
• Familiarity with state-of-the-art EDA tools for DFT, design, and verification.
• Basic knowledge of STA for DFT mode timing constraint development and exploration.

Who You Are:

• Excellent communicator with the ability to work effectively with cross-functional teams.
• Detail-oriented and driven by a passion for technology and continuous learning.
• Strong debugging skills and experience in scripting languages like Perl, TCL, and Python.
• Committed to fostering an inclusive and diverse work environment.
• Adaptable and eager to take on new challenges and responsibilities.

The Team You’ll Be A Part Of:

You will join a dynamic and innovative team focused on developing and implementing cutting-edge DFT methodologies to enhance the reliability and performance of our silicon chips. The team collaborates closely with cross-functional groups across geographies to drive technological advancements and achieve project goals. Together, we are committed to continuous learning, innovation, and fostering an inclusive work environment.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.