ASIC Digital Design, Sr Staff Engineer

ASIC Digital Design, Sr Staff Engineer

The candidate will be a key member of the Synopsys ARC Processor hardware team working on next-generation ARC processor Verification.

Individual contributor will be responsible for Verification of RTL design of microprocessor IP. Work with multi-site core teams. Review and improve verification test suites.

At minimum, a Bachelor’s/Master’s degree in engineering is required with 8+ years of digital design verification experience using UVM and System Verilog. Strong background in RISC architectures, AMBA (AHB, AXI) protocols are required. Working experience in RISC microprocessor IP design, an understanding of multi-core architectures and development techniques are a plus. Experience with multi-site development is helpful.

The successful candidate is expected to:

• Verification of embedded RISC microprocessor IP
• Write Verification plans based on High-level architecture and micro-architecture specifications of the design
• Develop standalone System Verilog testbenches to verify at Module Level (MLV)
• Working closely with the design/verification teams
• Hands on experience closing the Functional and code coverages
• Maintain our current processor product line and their derivative products
• Good written, oral and problem-solving skills desired along with good communication skills and inter-person skills
• Work with multi-site, multi-time zone, multi-cultural teams on various aspects of the product like design, implementation, physical design, verification

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.